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Nut/OS
5.0.5
API Reference
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Nut/OS
5.0.5
API Reference
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Defines | |
| #define | PERIPH_BB_BASE ((uint32_t)0x42000000) |
| #define | SRAM_BB_BASE ((uint32_t)0x22000000) |
| #define | SRAM_BASE ((uint32_t)0x20000000) |
| #define | PERIPH_BASE ((uint32_t)0x40000000) |
| #define | FSMC_R_BASE ((uint32_t)0xA0000000) |
| #define | APB1PERIPH_BASE PERIPH_BASE |
| #define | APB2PERIPH_BASE (PERIPH_BASE + 0x10000) |
| #define | AHBPERIPH_BASE (PERIPH_BASE + 0x20000) |
| #define | TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
| #define | TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
| #define | TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
| #define | TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
| #define | TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
| #define | TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
| #define | TIM12_BASE (APB1PERIPH_BASE + 0x1800) |
| #define | TIM13_BASE (APB1PERIPH_BASE + 0x1C00) |
| #define | TIM14_BASE (APB1PERIPH_BASE + 0x2000) |
| #define | RTC_BASE (APB1PERIPH_BASE + 0x2800) |
| #define | WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
| #define | IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
| #define | SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
| #define | SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
| #define | USART2_BASE (APB1PERIPH_BASE + 0x4400) |
| #define | USART3_BASE (APB1PERIPH_BASE + 0x4800) |
| #define | UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
| #define | UART5_BASE (APB1PERIPH_BASE + 0x5000) |
| #define | I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
| #define | I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
| #define | CAN1_BASE (APB1PERIPH_BASE + 0x6400) |
| #define | CAN2_BASE (APB1PERIPH_BASE + 0x6800) |
| #define | BKP_BASE (APB1PERIPH_BASE + 0x6C00) |
| #define | PWR_BASE (APB1PERIPH_BASE + 0x7000) |
| #define | DAC_BASE (APB1PERIPH_BASE + 0x7400) |
| #define | CEC_BASE (APB1PERIPH_BASE + 0x7800) |
| #define | AFIO_BASE (APB2PERIPH_BASE + 0x0000) |
| #define | EXTI_BASE (APB2PERIPH_BASE + 0x0400) |
| #define | GPIOA_BASE (APB2PERIPH_BASE + 0x0800) |
| #define | GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) |
| #define | GPIOC_BASE (APB2PERIPH_BASE + 0x1000) |
| #define | GPIOD_BASE (APB2PERIPH_BASE + 0x1400) |
| #define | GPIOE_BASE (APB2PERIPH_BASE + 0x1800) |
| #define | GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) |
| #define | GPIOG_BASE (APB2PERIPH_BASE + 0x2000) |
| #define | ADC1_BASE (APB2PERIPH_BASE + 0x2400) |
| #define | ADC2_BASE (APB2PERIPH_BASE + 0x2800) |
| #define | TIM1_BASE (APB2PERIPH_BASE + 0x2C00) |
| #define | SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
| #define | TIM8_BASE (APB2PERIPH_BASE + 0x3400) |
| #define | USART1_BASE (APB2PERIPH_BASE + 0x3800) |
| #define | ADC3_BASE (APB2PERIPH_BASE + 0x3C00) |
| #define | TIM15_BASE (APB2PERIPH_BASE + 0x4000) |
| #define | TIM16_BASE (APB2PERIPH_BASE + 0x4400) |
| #define | TIM17_BASE (APB2PERIPH_BASE + 0x4800) |
| #define | TIM9_BASE (APB2PERIPH_BASE + 0x4C00) |
| #define | TIM10_BASE (APB2PERIPH_BASE + 0x5000) |
| #define | TIM11_BASE (APB2PERIPH_BASE + 0x5400) |
| #define | SDIO_BASE (PERIPH_BASE + 0x18000) |
| #define | DMA1_BASE (AHBPERIPH_BASE + 0x0000) |
| #define | DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) |
| #define | DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) |
| #define | DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) |
| #define | DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) |
| #define | DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) |
| #define | DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) |
| #define | DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) |
| #define | DMA2_BASE (AHBPERIPH_BASE + 0x0400) |
| #define | DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) |
| #define | DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) |
| #define | DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) |
| #define | DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) |
| #define | DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) |
| #define | RCC_BASE (AHBPERIPH_BASE + 0x1000) |
| #define | CRC_BASE (AHBPERIPH_BASE + 0x3000) |
| #define | FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) |
| #define | OB_BASE ((uint32_t)0x1FFFF800) |
| #define | DEV_ESIG_BASE ((uint32_t)0x1FFFF7E0) |
| #define | ESIG ((ESIG_TypeDef *) DEV_ESIG_BASE) |
| #define | ETH_BASE (AHBPERIPH_BASE + 0x8000) |
| #define | ETH_MAC_BASE (ETH_BASE) |
| #define | ETH_MMC_BASE (ETH_BASE + 0x0100) |
| #define | ETH_PTP_BASE (ETH_BASE + 0x0700) |
| #define | ETH_DMA_BASE (ETH_BASE + 0x1000) |
| #define | FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) |
| #define | FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) |
| #define | FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) |
| #define | FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) |
| #define | FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) |
| #define | DBGMCU_BASE ((uint32_t)0xE0042000) |
| #define | FLASH_BASE ((uint32_t)0x08000000) |
| #define | SRAM_BASE ((uint32_t)0x20000000) |
| #define | PERIPH_BASE ((uint32_t)0x40000000) |
| #define | SRAM_BB_BASE ((uint32_t)0x22000000) |
| #define | PERIPH_BB_BASE ((uint32_t)0x42000000) |
| #define | FSMC_R_BASE ((uint32_t)0xA0000000) |
| #define | APB1PERIPH_BASE PERIPH_BASE |
| #define | APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) |
| #define | AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) |
| #define | AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) |
| #define | TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
| #define | TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
| #define | TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
| #define | TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
| #define | TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
| #define | TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
| #define | TIM12_BASE (APB1PERIPH_BASE + 0x1800) |
| #define | TIM13_BASE (APB1PERIPH_BASE + 0x1C00) |
| #define | TIM14_BASE (APB1PERIPH_BASE + 0x2000) |
| #define | RTC_BASE (APB1PERIPH_BASE + 0x2800) |
| #define | WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
| #define | IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
| #define | SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
| #define | SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
| #define | USART2_BASE (APB1PERIPH_BASE + 0x4400) |
| #define | USART3_BASE (APB1PERIPH_BASE + 0x4800) |
| #define | UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
| #define | UART5_BASE (APB1PERIPH_BASE + 0x5000) |
| #define | I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
| #define | I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
| #define | I2C3_BASE (APB1PERIPH_BASE + 0x5C00) |
| #define | CAN1_BASE (APB1PERIPH_BASE + 0x6400) |
| #define | CAN2_BASE (APB1PERIPH_BASE + 0x6800) |
| #define | PWR_BASE (APB1PERIPH_BASE + 0x7000) |
| #define | DAC_BASE (APB1PERIPH_BASE + 0x7400) |
| #define | TIM1_BASE (APB2PERIPH_BASE + 0x0000) |
| #define | TIM8_BASE (APB2PERIPH_BASE + 0x0400) |
| #define | USART1_BASE (APB2PERIPH_BASE + 0x1000) |
| #define | USART6_BASE (APB2PERIPH_BASE + 0x1400) |
| #define | ADC1_BASE (APB2PERIPH_BASE + 0x2000) |
| #define | ADC2_BASE (APB2PERIPH_BASE + 0x2100) |
| #define | ADC3_BASE (APB2PERIPH_BASE + 0x2200) |
| #define | ADC_BASE (APB2PERIPH_BASE + 0x2300) |
| #define | SDIO_BASE (APB2PERIPH_BASE + 0x2C00) |
| #define | SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
| #define | SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) |
| #define | EXTI_BASE (APB2PERIPH_BASE + 0x3C00) |
| #define | TIM9_BASE (APB2PERIPH_BASE + 0x4000) |
| #define | TIM10_BASE (APB2PERIPH_BASE + 0x4400) |
| #define | TIM11_BASE (APB2PERIPH_BASE + 0x4800) |
| #define | GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) |
| #define | GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) |
| #define | GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) |
| #define | GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) |
| #define | GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) |
| #define | GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) |
| #define | GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) |
| #define | GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) |
| #define | GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) |
| #define | CRC_BASE (AHB1PERIPH_BASE + 0x3000) |
| #define | RCC_BASE (AHB1PERIPH_BASE + 0x3800) |
| #define | FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) |
| #define | BKPSRAM_BASE (AHB1PERIPH_BASE + 0x4000) |
| #define | DMA1_BASE (AHB1PERIPH_BASE + 0x6000) |
| #define | DMA1_Stream0_BASE (DMA1_BASE + 0x010) |
| #define | DMA1_Stream1_BASE (DMA1_BASE + 0x028) |
| #define | DMA1_Stream2_BASE (DMA1_BASE + 0x040) |
| #define | DMA1_Stream3_BASE (DMA1_BASE + 0x058) |
| #define | DMA1_Stream4_BASE (DMA1_BASE + 0x070) |
| #define | DMA1_Stream5_BASE (DMA1_BASE + 0x088) |
| #define | DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) |
| #define | DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) |
| #define | DMA2_BASE (AHB1PERIPH_BASE + 0x6400) |
| #define | DMA2_Stream0_BASE (DMA2_BASE + 0x010) |
| #define | DMA2_Stream1_BASE (DMA2_BASE + 0x028) |
| #define | DMA2_Stream2_BASE (DMA2_BASE + 0x040) |
| #define | DMA2_Stream3_BASE (DMA2_BASE + 0x058) |
| #define | DMA2_Stream4_BASE (DMA2_BASE + 0x070) |
| #define | DMA2_Stream5_BASE (DMA2_BASE + 0x088) |
| #define | DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) |
| #define | DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) |
| #define | ETH_BASE (AHB1PERIPH_BASE + 0x8000) |
| #define | ETH_MAC_BASE (ETH_BASE) |
| #define | ETH_MMC_BASE (ETH_BASE + 0x0100) |
| #define | ETH_PTP_BASE (ETH_BASE + 0x0700) |
| #define | ETH_DMA_BASE (ETH_BASE + 0x1000) |
| #define | DCMI_BASE (AHB2PERIPH_BASE + 0x50000) |
| #define | CRYP_BASE (AHB2PERIPH_BASE + 0x60000) |
| #define | HASH_BASE (AHB2PERIPH_BASE + 0x60400) |
| #define | RNG_BASE (AHB2PERIPH_BASE + 0x60800) |
| #define | FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) |
| #define | FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) |
| #define | FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) |
| #define | FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) |
| #define | FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) |
| #define | DBGMCU_BASE ((uint32_t )0xE0042000) |
| #define | FLASH_BASE ((uint32_t)0x08000000) |
| #define | CCMDATARAM_BASE ((uint32_t)0x10000000) |
| #define | SRAM1_BASE ((uint32_t)0x20000000) |
| #define | SRAM2_BASE ((uint32_t)0x2001C000) |
| #define | PERIPH_BASE ((uint32_t)0x40000000) |
| #define | BKPSRAM_BASE ((uint32_t)0x40024000) |
| #define | FSMC_R_BASE ((uint32_t)0xA0000000) |
| #define | CCMDATARAM_BB_BASE ((uint32_t)0x12000000) |
| #define | SRAM1_BB_BASE ((uint32_t)0x22000000) |
| #define | SRAM2_BB_BASE ((uint32_t)0x2201C000) |
| #define | PERIPH_BB_BASE ((uint32_t)0x42000000) |
| #define | BKPSRAM_BB_BASE ((uint32_t)0x42024000) |
| #define | SRAM_BASE SRAM1_BASE |
| #define | SRAM_BB_BASE SRAM1_BB_BASE |
| #define | APB1PERIPH_BASE PERIPH_BASE |
| #define | APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) |
| #define | AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) |
| #define | AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) |
| #define | TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
| #define | TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
| #define | TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
| #define | TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
| #define | TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
| #define | TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
| #define | TIM12_BASE (APB1PERIPH_BASE + 0x1800) |
| #define | TIM13_BASE (APB1PERIPH_BASE + 0x1C00) |
| #define | TIM14_BASE (APB1PERIPH_BASE + 0x2000) |
| #define | RTC_BASE (APB1PERIPH_BASE + 0x2800) |
| #define | WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
| #define | IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
| #define | I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) |
| #define | SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
| #define | SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
| #define | I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) |
| #define | USART2_BASE (APB1PERIPH_BASE + 0x4400) |
| #define | USART3_BASE (APB1PERIPH_BASE + 0x4800) |
| #define | UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
| #define | UART5_BASE (APB1PERIPH_BASE + 0x5000) |
| #define | I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
| #define | I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
| #define | I2C3_BASE (APB1PERIPH_BASE + 0x5C00) |
| #define | CAN1_BASE (APB1PERIPH_BASE + 0x6400) |
| #define | CAN2_BASE (APB1PERIPH_BASE + 0x6800) |
| #define | PWR_BASE (APB1PERIPH_BASE + 0x7000) |
| #define | DAC_BASE (APB1PERIPH_BASE + 0x7400) |
| #define | TIM1_BASE (APB2PERIPH_BASE + 0x0000) |
| #define | TIM8_BASE (APB2PERIPH_BASE + 0x0400) |
| #define | USART1_BASE (APB2PERIPH_BASE + 0x1000) |
| #define | USART6_BASE (APB2PERIPH_BASE + 0x1400) |
| #define | ADC1_BASE (APB2PERIPH_BASE + 0x2000) |
| #define | ADC2_BASE (APB2PERIPH_BASE + 0x2100) |
| #define | ADC3_BASE (APB2PERIPH_BASE + 0x2200) |
| #define | ADC_BASE (APB2PERIPH_BASE + 0x2300) |
| #define | SDIO_BASE (APB2PERIPH_BASE + 0x2C00) |
| #define | SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
| #define | SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) |
| #define | EXTI_BASE (APB2PERIPH_BASE + 0x3C00) |
| #define | TIM9_BASE (APB2PERIPH_BASE + 0x4000) |
| #define | TIM10_BASE (APB2PERIPH_BASE + 0x4400) |
| #define | TIM11_BASE (APB2PERIPH_BASE + 0x4800) |
| #define | GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) |
| #define | GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) |
| #define | GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) |
| #define | GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) |
| #define | GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) |
| #define | GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) |
| #define | GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) |
| #define | GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) |
| #define | GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) |
| #define | CRC_BASE (AHB1PERIPH_BASE + 0x3000) |
| #define | RCC_BASE (AHB1PERIPH_BASE + 0x3800) |
| #define | FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) |
| #define | DMA1_BASE (AHB1PERIPH_BASE + 0x6000) |
| #define | DMA1_Stream0_BASE (DMA1_BASE + 0x010) |
| #define | DMA1_Stream1_BASE (DMA1_BASE + 0x028) |
| #define | DMA1_Stream2_BASE (DMA1_BASE + 0x040) |
| #define | DMA1_Stream3_BASE (DMA1_BASE + 0x058) |
| #define | DMA1_Stream4_BASE (DMA1_BASE + 0x070) |
| #define | DMA1_Stream5_BASE (DMA1_BASE + 0x088) |
| #define | DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) |
| #define | DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) |
| #define | DMA2_BASE (AHB1PERIPH_BASE + 0x6400) |
| #define | DMA2_Stream0_BASE (DMA2_BASE + 0x010) |
| #define | DMA2_Stream1_BASE (DMA2_BASE + 0x028) |
| #define | DMA2_Stream2_BASE (DMA2_BASE + 0x040) |
| #define | DMA2_Stream3_BASE (DMA2_BASE + 0x058) |
| #define | DMA2_Stream4_BASE (DMA2_BASE + 0x070) |
| #define | DMA2_Stream5_BASE (DMA2_BASE + 0x088) |
| #define | DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) |
| #define | DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) |
| #define | ETH_BASE (AHB1PERIPH_BASE + 0x8000) |
| #define | ETH_MAC_BASE (ETH_BASE) |
| #define | ETH_MMC_BASE (ETH_BASE + 0x0100) |
| #define | ETH_PTP_BASE (ETH_BASE + 0x0700) |
| #define | ETH_DMA_BASE (ETH_BASE + 0x1000) |
| #define | DCMI_BASE (AHB2PERIPH_BASE + 0x50000) |
| #define | CRYP_BASE (AHB2PERIPH_BASE + 0x60000) |
| #define | HASH_BASE (AHB2PERIPH_BASE + 0x60400) |
| #define | RNG_BASE (AHB2PERIPH_BASE + 0x60800) |
| #define | FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) |
| #define | FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) |
| #define | FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) |
| #define | FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) |
| #define | FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) |
| #define | DBGMCU_BASE ((uint32_t )0xE0042000) |
| #define | FLASH_BASE ((uint32_t)0x08000000) |
| #define | SRAM_BASE ((uint32_t)0x20000000) |
| #define | PERIPH_BASE ((uint32_t)0x40000000) |
| #define | SRAM_BB_BASE ((uint32_t)0x22000000) |
| #define | PERIPH_BB_BASE ((uint32_t)0x42000000) |
| #define | FSMC_R_BASE ((uint32_t)0xA0000000) |
| #define | APB1PERIPH_BASE PERIPH_BASE |
| #define | APB2PERIPH_BASE (PERIPH_BASE + 0x10000) |
| #define | AHBPERIPH_BASE (PERIPH_BASE + 0x20000) |
| #define | TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
| #define | TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
| #define | TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
| #define | TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
| #define | TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
| #define | TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
| #define | LCD_BASE (APB1PERIPH_BASE + 0x2400) |
| #define | RTC_BASE (APB1PERIPH_BASE + 0x2800) |
| #define | WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
| #define | IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
| #define | SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
| #define | SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
| #define | USART2_BASE (APB1PERIPH_BASE + 0x4400) |
| #define | USART3_BASE (APB1PERIPH_BASE + 0x4800) |
| #define | UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
| #define | UART5_BASE (APB1PERIPH_BASE + 0x5000) |
| #define | I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
| #define | I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
| #define | PWR_BASE (APB1PERIPH_BASE + 0x7000) |
| #define | DAC_BASE (APB1PERIPH_BASE + 0x7400) |
| #define | COMP_BASE (APB1PERIPH_BASE + 0x7C00) |
| #define | RI_BASE (APB1PERIPH_BASE + 0x7C04) |
| #define | OPAMP_BASE (APB1PERIPH_BASE + 0x7C5C) |
| #define | SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) |
| #define | EXTI_BASE (APB2PERIPH_BASE + 0x0400) |
| #define | TIM9_BASE (APB2PERIPH_BASE + 0x0800) |
| #define | TIM10_BASE (APB2PERIPH_BASE + 0x0C00) |
| #define | TIM11_BASE (APB2PERIPH_BASE + 0x1000) |
| #define | ADC1_BASE (APB2PERIPH_BASE + 0x2400) |
| #define | ADC_BASE (APB2PERIPH_BASE + 0x2700) |
| #define | SDIO_BASE (APB2PERIPH_BASE + 0x2C00) |
| #define | SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
| #define | USART1_BASE (APB2PERIPH_BASE + 0x3800) |
| #define | GPIOA_BASE (AHBPERIPH_BASE + 0x0000) |
| #define | GPIOB_BASE (AHBPERIPH_BASE + 0x0400) |
| #define | GPIOC_BASE (AHBPERIPH_BASE + 0x0800) |
| #define | GPIOD_BASE (AHBPERIPH_BASE + 0x0C00) |
| #define | GPIOE_BASE (AHBPERIPH_BASE + 0x1000) |
| #define | GPIOH_BASE (AHBPERIPH_BASE + 0x1400) |
| #define | GPIOF_BASE (AHBPERIPH_BASE + 0x1800) |
| #define | GPIOG_BASE (AHBPERIPH_BASE + 0x1C00) |
| #define | CRC_BASE (AHBPERIPH_BASE + 0x3000) |
| #define | RCC_BASE (AHBPERIPH_BASE + 0x3800) |
| #define | FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) |
| #define | OB_BASE ((uint32_t)0x1FF80000) |
| #define | DMA1_BASE (AHBPERIPH_BASE + 0x6000) |
| #define | DMA1_Channel1_BASE (DMA1_BASE + 0x0008) |
| #define | DMA1_Channel2_BASE (DMA1_BASE + 0x001C) |
| #define | DMA1_Channel3_BASE (DMA1_BASE + 0x0030) |
| #define | DMA1_Channel4_BASE (DMA1_BASE + 0x0044) |
| #define | DMA1_Channel5_BASE (DMA1_BASE + 0x0058) |
| #define | DMA1_Channel6_BASE (DMA1_BASE + 0x006C) |
| #define | DMA1_Channel7_BASE (DMA1_BASE + 0x0080) |
| #define | DMA2_BASE (AHBPERIPH_BASE + 0x6400) |
| #define | DMA2_Channel1_BASE (DMA2_BASE + 0x0008) |
| #define | DMA2_Channel2_BASE (DMA2_BASE + 0x001C) |
| #define | DMA2_Channel3_BASE (DMA2_BASE + 0x0030) |
| #define | DMA2_Channel4_BASE (DMA2_BASE + 0x0044) |
| #define | DMA2_Channel5_BASE (DMA2_BASE + 0x0058) |
| #define | AES_BASE ((uint32_t)0x50060000) |
| #define | FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) |
| #define | FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) |
| #define | DBGMCU_BASE ((uint32_t)0xE0042000) |
| #define PERIPH_BB_BASE ((uint32_t)0x42000000) |
Peripheral base address in the alias region
| #define SRAM_BB_BASE ((uint32_t)0x22000000) |
SRAM base address in the alias region
| #define SRAM_BASE ((uint32_t)0x20000000) |
SRAM base address in the bit-band region
Referenced by SystemInit().
| #define PERIPH_BASE ((uint32_t)0x40000000) |
Peripheral base address in the bit-band region
Referenced by DMA_Setup().
| #define FSMC_R_BASE ((uint32_t)0xA0000000) |
FSMC registers base address Peripheral memory map
| #define APB1PERIPH_BASE PERIPH_BASE |
| #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) |
| #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) |
| #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
| #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
| #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
| #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
| #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
| #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
| #define TIM12_BASE (APB1PERIPH_BASE + 0x1800) |
| #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) |
| #define TIM14_BASE (APB1PERIPH_BASE + 0x2000) |
| #define RTC_BASE (APB1PERIPH_BASE + 0x2800) |
| #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
| #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
| #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
| #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
| #define USART2_BASE (APB1PERIPH_BASE + 0x4400) |
| #define USART3_BASE (APB1PERIPH_BASE + 0x4800) |
| #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
| #define UART5_BASE (APB1PERIPH_BASE + 0x5000) |
| #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
Referenced by NutRegisterTwiBus().
| #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
Referenced by NutRegisterTwiBus().
| #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) |
Referenced by CanAddFilter().
| #define CAN2_BASE (APB1PERIPH_BASE + 0x6800) |
| #define BKP_BASE (APB1PERIPH_BASE + 0x6C00) |
| #define PWR_BASE (APB1PERIPH_BASE + 0x7000) |
| #define DAC_BASE (APB1PERIPH_BASE + 0x7400) |
| #define CEC_BASE (APB1PERIPH_BASE + 0x7800) |
| #define AFIO_BASE (APB2PERIPH_BASE + 0x0000) |
| #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) |
| #define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) |
Referenced by GpioPinConfigSet(), and GpioPortConfigSet().
| #define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) |
| #define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) |
| #define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) |
| #define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) |
| #define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) |
| #define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) |
| #define ADC1_BASE (APB2PERIPH_BASE + 0x2400) |
| #define ADC2_BASE (APB2PERIPH_BASE + 0x2800) |
| #define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) |
| #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
| #define TIM8_BASE (APB2PERIPH_BASE + 0x3400) |
| #define USART1_BASE (APB2PERIPH_BASE + 0x3800) |
| #define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) |
| #define TIM15_BASE (APB2PERIPH_BASE + 0x4000) |
| #define TIM16_BASE (APB2PERIPH_BASE + 0x4400) |
| #define TIM17_BASE (APB2PERIPH_BASE + 0x4800) |
| #define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) |
| #define TIM10_BASE (APB2PERIPH_BASE + 0x5000) |
| #define TIM11_BASE (APB2PERIPH_BASE + 0x5400) |
| #define SDIO_BASE (PERIPH_BASE + 0x18000) |
| #define DMA1_BASE (AHBPERIPH_BASE + 0x0000) |
Referenced by DMA_ClearFlag(), DMA_Disable(), DMA_Enable(), DMA_GetFlag(), DMA_IrqMask(), and DMA_Setup().
| #define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) |
| #define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) |
| #define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) |
| #define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) |
| #define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) |
| #define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) |
| #define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) |
| #define DMA2_BASE (AHBPERIPH_BASE + 0x0400) |
Referenced by DMA_ClearFlag(), DMA_Disable(), DMA_Enable(), DMA_GetFlag(), DMA_IrqMask(), and DMA_Setup().
| #define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) |
| #define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) |
| #define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) |
| #define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) |
| #define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) |
| #define RCC_BASE (AHBPERIPH_BASE + 0x1000) |
Referenced by DMA_Init(), GpioPinConfigSet(), SetPllClockSource(), Stm32CanHw1Init(), and Stm32CanHw2Init().
| #define CRC_BASE (AHBPERIPH_BASE + 0x3000) |
| #define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) |
Flash registers base address
| #define OB_BASE ((uint32_t)0x1FFFF800) |
Flash Option Bytes base address
| #define DEV_ESIG_BASE ((uint32_t)0x1FFFF7E0) |
Device Electronic Signature base address
| #define ESIG ((ESIG_TypeDef *) DEV_ESIG_BASE) |
| #define ETH_BASE (AHBPERIPH_BASE + 0x8000) |
| #define ETH_MAC_BASE (ETH_BASE) |
| #define ETH_MMC_BASE (ETH_BASE + 0x0100) |
| #define ETH_PTP_BASE (ETH_BASE + 0x0700) |
| #define ETH_DMA_BASE (ETH_BASE + 0x1000) |
| #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) |
FSMC Bank1 registers base address
| #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) |
FSMC Bank1E registers base address
| #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) |
FSMC Bank2 registers base address
| #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) |
FSMC Bank3 registers base address
| #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) |
FSMC Bank4 registers base address
| #define DBGMCU_BASE ((uint32_t)0xE0042000) |
Debug MCU registers base address
| #define FLASH_BASE ((uint32_t)0x08000000) |
FLASH base address in the alias region
| #define SRAM_BASE ((uint32_t)0x20000000) |
SRAM base address in the alias region
| #define PERIPH_BASE ((uint32_t)0x40000000) |
Peripheral base address in the alias region
| #define SRAM_BB_BASE ((uint32_t)0x22000000) |
SRAM base address in the bit-band region
| #define PERIPH_BB_BASE ((uint32_t)0x42000000) |
Peripheral base address in the bit-band region
| #define FSMC_R_BASE ((uint32_t)0xA0000000) |
FSMC registers base address Peripheral memory map
| #define APB1PERIPH_BASE PERIPH_BASE |
| #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) |
| #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) |
| #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) |
APB1 peripherals
| #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
| #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
| #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
| #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
| #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
| #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
| #define TIM12_BASE (APB1PERIPH_BASE + 0x1800) |
| #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) |
| #define TIM14_BASE (APB1PERIPH_BASE + 0x2000) |
| #define RTC_BASE (APB1PERIPH_BASE + 0x2800) |
| #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
| #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
| #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
| #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
| #define USART2_BASE (APB1PERIPH_BASE + 0x4400) |
| #define USART3_BASE (APB1PERIPH_BASE + 0x4800) |
| #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
| #define UART5_BASE (APB1PERIPH_BASE + 0x5000) |
| #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
| #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
| #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) |
| #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) |
| #define CAN2_BASE (APB1PERIPH_BASE + 0x6800) |
| #define PWR_BASE (APB1PERIPH_BASE + 0x7000) |
| #define DAC_BASE (APB1PERIPH_BASE + 0x7400) |
APB2 peripherals
| #define TIM1_BASE (APB2PERIPH_BASE + 0x0000) |
| #define TIM8_BASE (APB2PERIPH_BASE + 0x0400) |
| #define USART1_BASE (APB2PERIPH_BASE + 0x1000) |
| #define USART6_BASE (APB2PERIPH_BASE + 0x1400) |
| #define ADC1_BASE (APB2PERIPH_BASE + 0x2000) |
| #define ADC2_BASE (APB2PERIPH_BASE + 0x2100) |
| #define ADC3_BASE (APB2PERIPH_BASE + 0x2200) |
| #define ADC_BASE (APB2PERIPH_BASE + 0x2300) |
| #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) |
| #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
| #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) |
Referenced by GpioPinConfigSet().
| #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) |
| #define TIM9_BASE (APB2PERIPH_BASE + 0x4000) |
| #define TIM10_BASE (APB2PERIPH_BASE + 0x4400) |
| #define TIM11_BASE (APB2PERIPH_BASE + 0x4800) |
AHB1 peripherals
| #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) |
| #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) |
| #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) |
| #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) |
| #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) |
| #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) |
| #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) |
| #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) |
| #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) |
| #define CRC_BASE (AHB1PERIPH_BASE + 0x3000) |
| #define RCC_BASE (AHB1PERIPH_BASE + 0x3800) |
| #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) |
| #define BKPSRAM_BASE (AHB1PERIPH_BASE + 0x4000) |
| #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) |
| #define DMA1_Stream0_BASE (DMA1_BASE + 0x010) |
| #define DMA1_Stream1_BASE (DMA1_BASE + 0x028) |
| #define DMA1_Stream2_BASE (DMA1_BASE + 0x040) |
| #define DMA1_Stream3_BASE (DMA1_BASE + 0x058) |
| #define DMA1_Stream4_BASE (DMA1_BASE + 0x070) |
| #define DMA1_Stream5_BASE (DMA1_BASE + 0x088) |
| #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) |
| #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) |
| #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) |
| #define DMA2_Stream0_BASE (DMA2_BASE + 0x010) |
| #define DMA2_Stream1_BASE (DMA2_BASE + 0x028) |
| #define DMA2_Stream2_BASE (DMA2_BASE + 0x040) |
| #define DMA2_Stream3_BASE (DMA2_BASE + 0x058) |
| #define DMA2_Stream4_BASE (DMA2_BASE + 0x070) |
| #define DMA2_Stream5_BASE (DMA2_BASE + 0x088) |
| #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) |
| #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) |
| #define ETH_BASE (AHB1PERIPH_BASE + 0x8000) |
| #define ETH_MAC_BASE (ETH_BASE) |
| #define ETH_MMC_BASE (ETH_BASE + 0x0100) |
| #define ETH_PTP_BASE (ETH_BASE + 0x0700) |
| #define ETH_DMA_BASE (ETH_BASE + 0x1000) |
AHB2 peripherals
| #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) |
| #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) |
| #define HASH_BASE (AHB2PERIPH_BASE + 0x60400) |
| #define RNG_BASE (AHB2PERIPH_BASE + 0x60800) |
FSMC Bankx registers base address
| #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) |
| #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) |
| #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) |
| #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) |
| #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) |
| #define DBGMCU_BASE ((uint32_t )0xE0042000) |
| #define FLASH_BASE ((uint32_t)0x08000000) |
FLASH(up to 1 MB) base address in the alias region
| #define CCMDATARAM_BASE ((uint32_t)0x10000000) |
CCM(core coupled memory) data RAM(64 KB) base address in the alias region
| #define SRAM1_BASE ((uint32_t)0x20000000) |
SRAM1(112 KB) base address in the alias region
| #define SRAM2_BASE ((uint32_t)0x2001C000) |
SRAM2(16 KB) base address in the alias region
| #define PERIPH_BASE ((uint32_t)0x40000000) |
Peripheral base address in the alias region
| #define BKPSRAM_BASE ((uint32_t)0x40024000) |
Backup SRAM(4 KB) base address in the alias region
| #define FSMC_R_BASE ((uint32_t)0xA0000000) |
FSMC registers base address
| #define CCMDATARAM_BB_BASE ((uint32_t)0x12000000) |
CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region
| #define SRAM1_BB_BASE ((uint32_t)0x22000000) |
SRAM1(112 KB) base address in the bit-band region
| #define SRAM2_BB_BASE ((uint32_t)0x2201C000) |
SRAM2(16 KB) base address in the bit-band region
| #define PERIPH_BB_BASE ((uint32_t)0x42000000) |
Peripheral base address in the bit-band region
| #define BKPSRAM_BB_BASE ((uint32_t)0x42024000) |
Backup SRAM(4 KB) base address in the bit-band region
| #define SRAM_BASE SRAM1_BASE |
| #define SRAM_BB_BASE SRAM1_BB_BASE |
Peripheral memory map
| #define APB1PERIPH_BASE PERIPH_BASE |
| #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000) |
| #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000) |
| #define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000) |
APB1 peripherals
| #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
| #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
| #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
| #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
| #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
| #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
| #define TIM12_BASE (APB1PERIPH_BASE + 0x1800) |
| #define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) |
| #define TIM14_BASE (APB1PERIPH_BASE + 0x2000) |
| #define RTC_BASE (APB1PERIPH_BASE + 0x2800) |
| #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
| #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
| #define I2S2ext_BASE (APB1PERIPH_BASE + 0x3400) |
| #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
| #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
| #define I2S3ext_BASE (APB1PERIPH_BASE + 0x4000) |
| #define USART2_BASE (APB1PERIPH_BASE + 0x4400) |
| #define USART3_BASE (APB1PERIPH_BASE + 0x4800) |
| #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
| #define UART5_BASE (APB1PERIPH_BASE + 0x5000) |
| #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
| #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
| #define I2C3_BASE (APB1PERIPH_BASE + 0x5C00) |
| #define CAN1_BASE (APB1PERIPH_BASE + 0x6400) |
| #define CAN2_BASE (APB1PERIPH_BASE + 0x6800) |
| #define PWR_BASE (APB1PERIPH_BASE + 0x7000) |
| #define DAC_BASE (APB1PERIPH_BASE + 0x7400) |
APB2 peripherals
| #define TIM1_BASE (APB2PERIPH_BASE + 0x0000) |
| #define TIM8_BASE (APB2PERIPH_BASE + 0x0400) |
| #define USART1_BASE (APB2PERIPH_BASE + 0x1000) |
| #define USART6_BASE (APB2PERIPH_BASE + 0x1400) |
| #define ADC1_BASE (APB2PERIPH_BASE + 0x2000) |
| #define ADC2_BASE (APB2PERIPH_BASE + 0x2100) |
| #define ADC3_BASE (APB2PERIPH_BASE + 0x2200) |
| #define ADC_BASE (APB2PERIPH_BASE + 0x2300) |
| #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) |
| #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
| #define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800) |
| #define EXTI_BASE (APB2PERIPH_BASE + 0x3C00) |
| #define TIM9_BASE (APB2PERIPH_BASE + 0x4000) |
| #define TIM10_BASE (APB2PERIPH_BASE + 0x4400) |
| #define TIM11_BASE (APB2PERIPH_BASE + 0x4800) |
AHB1 peripherals
| #define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000) |
| #define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400) |
| #define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800) |
| #define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00) |
| #define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000) |
| #define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400) |
| #define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800) |
| #define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00) |
| #define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000) |
| #define CRC_BASE (AHB1PERIPH_BASE + 0x3000) |
| #define RCC_BASE (AHB1PERIPH_BASE + 0x3800) |
| #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00) |
| #define DMA1_BASE (AHB1PERIPH_BASE + 0x6000) |
| #define DMA1_Stream0_BASE (DMA1_BASE + 0x010) |
| #define DMA1_Stream1_BASE (DMA1_BASE + 0x028) |
| #define DMA1_Stream2_BASE (DMA1_BASE + 0x040) |
| #define DMA1_Stream3_BASE (DMA1_BASE + 0x058) |
| #define DMA1_Stream4_BASE (DMA1_BASE + 0x070) |
| #define DMA1_Stream5_BASE (DMA1_BASE + 0x088) |
| #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0) |
| #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8) |
| #define DMA2_BASE (AHB1PERIPH_BASE + 0x6400) |
| #define DMA2_Stream0_BASE (DMA2_BASE + 0x010) |
| #define DMA2_Stream1_BASE (DMA2_BASE + 0x028) |
| #define DMA2_Stream2_BASE (DMA2_BASE + 0x040) |
| #define DMA2_Stream3_BASE (DMA2_BASE + 0x058) |
| #define DMA2_Stream4_BASE (DMA2_BASE + 0x070) |
| #define DMA2_Stream5_BASE (DMA2_BASE + 0x088) |
| #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0) |
| #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8) |
| #define ETH_BASE (AHB1PERIPH_BASE + 0x8000) |
| #define ETH_MAC_BASE (ETH_BASE) |
| #define ETH_MMC_BASE (ETH_BASE + 0x0100) |
| #define ETH_PTP_BASE (ETH_BASE + 0x0700) |
| #define ETH_DMA_BASE (ETH_BASE + 0x1000) |
AHB2 peripherals
| #define DCMI_BASE (AHB2PERIPH_BASE + 0x50000) |
| #define CRYP_BASE (AHB2PERIPH_BASE + 0x60000) |
| #define HASH_BASE (AHB2PERIPH_BASE + 0x60400) |
| #define RNG_BASE (AHB2PERIPH_BASE + 0x60800) |
FSMC Bankx registers base address
| #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) |
| #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) |
| #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) |
| #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) |
| #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) |
| #define DBGMCU_BASE ((uint32_t )0xE0042000) |
| #define FLASH_BASE ((uint32_t)0x08000000) |
FLASH base address in the alias region
| #define SRAM_BASE ((uint32_t)0x20000000) |
SRAM base address in the alias region
| #define PERIPH_BASE ((uint32_t)0x40000000) |
Peripheral base address in the alias region
| #define SRAM_BB_BASE ((uint32_t)0x22000000) |
SRAM base address in the bit-band region
| #define PERIPH_BB_BASE ((uint32_t)0x42000000) |
Peripheral base address in the bit-band region
| #define FSMC_R_BASE ((uint32_t)0xA0000000) |
FSMC registers base address Peripheral memory map
| #define APB1PERIPH_BASE PERIPH_BASE |
| #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) |
| #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) |
| #define TIM2_BASE (APB1PERIPH_BASE + 0x0000) |
| #define TIM3_BASE (APB1PERIPH_BASE + 0x0400) |
| #define TIM4_BASE (APB1PERIPH_BASE + 0x0800) |
| #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) |
| #define TIM6_BASE (APB1PERIPH_BASE + 0x1000) |
| #define TIM7_BASE (APB1PERIPH_BASE + 0x1400) |
| #define LCD_BASE (APB1PERIPH_BASE + 0x2400) |
| #define RTC_BASE (APB1PERIPH_BASE + 0x2800) |
| #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) |
| #define IWDG_BASE (APB1PERIPH_BASE + 0x3000) |
| #define SPI2_BASE (APB1PERIPH_BASE + 0x3800) |
| #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00) |
| #define USART2_BASE (APB1PERIPH_BASE + 0x4400) |
| #define USART3_BASE (APB1PERIPH_BASE + 0x4800) |
| #define UART4_BASE (APB1PERIPH_BASE + 0x4C00) |
| #define UART5_BASE (APB1PERIPH_BASE + 0x5000) |
| #define I2C1_BASE (APB1PERIPH_BASE + 0x5400) |
| #define I2C2_BASE (APB1PERIPH_BASE + 0x5800) |
| #define PWR_BASE (APB1PERIPH_BASE + 0x7000) |
| #define DAC_BASE (APB1PERIPH_BASE + 0x7400) |
| #define COMP_BASE (APB1PERIPH_BASE + 0x7C00) |
| #define RI_BASE (APB1PERIPH_BASE + 0x7C04) |
| #define OPAMP_BASE (APB1PERIPH_BASE + 0x7C5C) |
| #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000) |
| #define EXTI_BASE (APB2PERIPH_BASE + 0x0400) |
| #define TIM9_BASE (APB2PERIPH_BASE + 0x0800) |
| #define TIM10_BASE (APB2PERIPH_BASE + 0x0C00) |
| #define TIM11_BASE (APB2PERIPH_BASE + 0x1000) |
| #define ADC1_BASE (APB2PERIPH_BASE + 0x2400) |
| #define ADC_BASE (APB2PERIPH_BASE + 0x2700) |
| #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00) |
| #define SPI1_BASE (APB2PERIPH_BASE + 0x3000) |
| #define USART1_BASE (APB2PERIPH_BASE + 0x3800) |
| #define GPIOA_BASE (AHBPERIPH_BASE + 0x0000) |
| #define GPIOB_BASE (AHBPERIPH_BASE + 0x0400) |
| #define GPIOC_BASE (AHBPERIPH_BASE + 0x0800) |
| #define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00) |
| #define GPIOE_BASE (AHBPERIPH_BASE + 0x1000) |
| #define GPIOH_BASE (AHBPERIPH_BASE + 0x1400) |
| #define GPIOF_BASE (AHBPERIPH_BASE + 0x1800) |
| #define GPIOG_BASE (AHBPERIPH_BASE + 0x1C00) |
| #define CRC_BASE (AHBPERIPH_BASE + 0x3000) |
| #define RCC_BASE (AHBPERIPH_BASE + 0x3800) |
| #define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) |
FLASH registers base address
| #define OB_BASE ((uint32_t)0x1FF80000) |
FLASH Option Bytes base address
| #define DMA1_BASE (AHBPERIPH_BASE + 0x6000) |
| #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008) |
| #define DMA1_Channel2_BASE (DMA1_BASE + 0x001C) |
| #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030) |
| #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044) |
| #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058) |
| #define DMA1_Channel6_BASE (DMA1_BASE + 0x006C) |
| #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080) |
| #define DMA2_BASE (AHBPERIPH_BASE + 0x6400) |
| #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008) |
| #define DMA2_Channel2_BASE (DMA2_BASE + 0x001C) |
| #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030) |
| #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044) |
| #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058) |
| #define AES_BASE ((uint32_t)0x50060000) |
| #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) |
FSMC Bank1 registers base address
| #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) |
FSMC Bank1E registers base address
| #define DBGMCU_BASE ((uint32_t)0xE0042000) |
Debug MCU registers base address