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Nut/OS
5.0.5
API Reference
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Nut/OS
5.0.5
API Reference
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Defines | |
| #define | RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
| #define | CR_OFFSET (RCC_OFFSET + 0x00) |
| #define | HSION_BitNumber 0x00 |
| #define | CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) |
| #define | PLLON_BitNumber 0x18 |
| #define | CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) |
| #define | CSSON_BitNumber 0x13 |
| #define | CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) |
| #define | CFGR_OFFSET (RCC_OFFSET + 0x04) |
| #define | USBPRE_BitNumber 0x16 |
| #define | CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) |
| #define | BDCR_OFFSET (RCC_OFFSET + 0x20) |
| #define | RTCEN_BitNumber 0x0F |
| #define | BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) |
| #define | BDRST_BitNumber 0x10 |
| #define | BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) |
| #define | CSR_OFFSET (RCC_OFFSET + 0x24) |
| #define | LSION_BitNumber 0x00 |
| #define | CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) |
| #define | CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) |
| #define | CR_HSEBYP_Set ((uint32_t)0x00040000) |
| #define | CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) |
| #define | CR_HSEON_Set ((uint32_t)0x00010000) |
| #define | CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) |
| #define | CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) |
| #define | CFGR_PLLMull_Mask ((uint32_t)0x003C0000) |
| #define | CFGR_PLLSRC_Mask ((uint32_t)0x00010000) |
| #define | CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) |
| #define | CFGR_SWS_Mask ((uint32_t)0x0000000C) |
| #define | CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) |
| #define | CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) |
| #define | CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) |
| #define | CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) |
| #define | CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) |
| #define | CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) |
| #define | CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) |
| #define | CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) |
| #define | CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) |
| #define | CSR_RMVF_Set ((uint32_t)0x01000000) |
| #define | FLAG_Mask ((uint8_t)0x1F) |
| #define | CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) |
| #define | CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) |
| #define | CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) |
| #define | BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) |
| #define | HSEStartUp_TimeOut ((uint16_t)0x0500) |
| #define | RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
| #define | CR_OFFSET (RCC_OFFSET + 0x00) |
| #define | HSION_BitNumber 0x00 |
| #define | CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) |
| #define | PLLON_BitNumber 0x18 |
| #define | CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) |
| #define | CSSON_BitNumber 0x13 |
| #define | CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) |
| #define | CFGR_OFFSET (RCC_OFFSET + 0x04) |
| #define | USBPRE_BitNumber 0x16 |
| #define | CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) |
| #define | BDCR_OFFSET (RCC_OFFSET + 0x20) |
| #define | RTCEN_BitNumber 0x0F |
| #define | BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) |
| #define | BDRST_BitNumber 0x10 |
| #define | BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) |
| #define | CSR_OFFSET (RCC_OFFSET + 0x24) |
| #define | LSION_BitNumber 0x00 |
| #define | CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) |
| #define | CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) |
| #define | CR_HSEBYP_Set ((uint32_t)0x00040000) |
| #define | CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) |
| #define | CR_HSEON_Set ((uint32_t)0x00010000) |
| #define | CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) |
| #define | CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) |
| #define | CFGR_PLLMull_Mask ((uint32_t)0x003C0000) |
| #define | CFGR_PLLSRC_Mask ((uint32_t)0x00010000) |
| #define | CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) |
| #define | CFGR_SWS_Mask ((uint32_t)0x0000000C) |
| #define | CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) |
| #define | CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) |
| #define | CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) |
| #define | CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) |
| #define | CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) |
| #define | CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) |
| #define | CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) |
| #define | CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) |
| #define | CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) |
| #define | CSR_RMVF_Set ((uint32_t)0x01000000) |
| #define | FLAG_Mask ((uint8_t)0x1F) |
| #define | CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) |
| #define | CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) |
| #define | CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) |
| #define | BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) |
| #define | HSEStartUp_TimeOut ((uint16_t)0x0500) |
| #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
| #define CR_OFFSET (RCC_OFFSET + 0x00) |
| #define HSION_BitNumber 0x00 |
| #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) |
Referenced by RCC_HSICmd().
| #define PLLON_BitNumber 0x18 |
| #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) |
Referenced by RCC_PLLCmd().
| #define CSSON_BitNumber 0x13 |
| #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) |
Referenced by RCC_ClockSecuritySystemCmd().
| #define CFGR_OFFSET (RCC_OFFSET + 0x04) |
| #define USBPRE_BitNumber 0x16 |
| #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) |
Referenced by RCC_USBCLKConfig().
| #define BDCR_OFFSET (RCC_OFFSET + 0x20) |
| #define RTCEN_BitNumber 0x0F |
| #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) |
Referenced by RCC_RTCCLKCmd().
| #define BDRST_BitNumber 0x10 |
| #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) |
Referenced by RCC_BackupResetCmd().
| #define CSR_OFFSET (RCC_OFFSET + 0x24) |
| #define LSION_BitNumber 0x00 |
| #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) |
Referenced by RCC_LSICmd().
| #define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) |
Referenced by RCC_HSEConfig().
| #define CR_HSEBYP_Set ((uint32_t)0x00040000) |
Referenced by RCC_HSEConfig().
| #define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) |
Referenced by RCC_HSEConfig().
| #define CR_HSEON_Set ((uint32_t)0x00010000) |
Referenced by RCC_HSEConfig().
| #define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) |
Referenced by RCC_AdjustHSICalibrationValue().
| #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) |
Referenced by RCC_PLLConfig().
| #define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) |
Referenced by RCC_GetClocksFreq().
| #define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) |
Referenced by RCC_GetClocksFreq().
| #define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) |
Referenced by RCC_GetClocksFreq().
| #define CFGR_SWS_Mask ((uint32_t)0x0000000C) |
Referenced by RCC_GetClocksFreq(), and RCC_GetSYSCLKSource().
| #define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) |
Referenced by RCC_SYSCLKConfig().
| #define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) |
Referenced by RCC_HCLKConfig().
| #define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) |
Referenced by RCC_GetClocksFreq().
| #define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) |
Referenced by RCC_PCLK1Config().
| #define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) |
Referenced by RCC_GetClocksFreq().
| #define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) |
Referenced by RCC_PCLK2Config().
| #define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) |
Referenced by RCC_GetClocksFreq().
| #define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) |
Referenced by RCC_ADCCLKConfig().
| #define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) |
Referenced by RCC_GetClocksFreq().
| #define CSR_RMVF_Set ((uint32_t)0x01000000) |
Referenced by RCC_ClearFlag().
| #define FLAG_Mask ((uint8_t)0x1F) |
Referenced by RCC_GetFlagStatus().
| #define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) |
Referenced by RCC_ITConfig().
| #define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) |
Referenced by RCC_ClearITPendingBit().
| #define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) |
Referenced by RCC_MCOConfig().
| #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) |
Referenced by RCC_LSEConfig().
| #define HSEStartUp_TimeOut ((uint16_t)0x0500) |
| #define RCC_OFFSET (RCC_BASE - PERIPH_BASE) |
| #define CR_OFFSET (RCC_OFFSET + 0x00) |
| #define HSION_BitNumber 0x00 |
| #define CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4)) |
Referenced by RCC_HSICmd().
| #define PLLON_BitNumber 0x18 |
| #define CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4)) |
Referenced by RCC_PLLCmd().
| #define CSSON_BitNumber 0x13 |
| #define CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4)) |
Referenced by RCC_ClockSecuritySystemCmd().
| #define CFGR_OFFSET (RCC_OFFSET + 0x04) |
| #define USBPRE_BitNumber 0x16 |
| #define CFGR_USBPRE_BB (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (USBPRE_BitNumber * 4)) |
Referenced by RCC_USBCLKConfig().
| #define BDCR_OFFSET (RCC_OFFSET + 0x20) |
| #define RTCEN_BitNumber 0x0F |
| #define BDCR_RTCEN_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4)) |
Referenced by RCC_RTCCLKCmd().
| #define BDRST_BitNumber 0x10 |
| #define BDCR_BDRST_BB (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4)) |
Referenced by RCC_BackupResetCmd().
| #define CSR_OFFSET (RCC_OFFSET + 0x24) |
| #define LSION_BitNumber 0x00 |
| #define CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4)) |
Referenced by RCC_LSICmd().
| #define CR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) |
Referenced by RCC_HSEConfig().
| #define CR_HSEBYP_Set ((uint32_t)0x00040000) |
Referenced by RCC_HSEConfig().
| #define CR_HSEON_Reset ((uint32_t)0xFFFEFFFF) |
Referenced by RCC_HSEConfig().
| #define CR_HSEON_Set ((uint32_t)0x00010000) |
Referenced by RCC_HSEConfig().
| #define CR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) |
Referenced by RCC_AdjustHSICalibrationValue().
| #define CFGR_PLL_Mask ((uint32_t)0xFFC0FFFF) |
Referenced by RCC_PLLConfig().
| #define CFGR_PLLMull_Mask ((uint32_t)0x003C0000) |
Referenced by RCC_GetClocksFreq().
| #define CFGR_PLLSRC_Mask ((uint32_t)0x00010000) |
Referenced by RCC_GetClocksFreq().
| #define CFGR_PLLXTPRE_Mask ((uint32_t)0x00020000) |
Referenced by RCC_GetClocksFreq().
| #define CFGR_SWS_Mask ((uint32_t)0x0000000C) |
Referenced by RCC_GetClocksFreq(), and RCC_GetSYSCLKSource().
| #define CFGR_SW_Mask ((uint32_t)0xFFFFFFFC) |
Referenced by RCC_SYSCLKConfig().
| #define CFGR_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) |
Referenced by RCC_HCLKConfig().
| #define CFGR_HPRE_Set_Mask ((uint32_t)0x000000F0) |
Referenced by RCC_GetClocksFreq().
| #define CFGR_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) |
Referenced by RCC_PCLK1Config().
| #define CFGR_PPRE1_Set_Mask ((uint32_t)0x00000700) |
Referenced by RCC_GetClocksFreq().
| #define CFGR_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) |
Referenced by RCC_PCLK2Config().
| #define CFGR_PPRE2_Set_Mask ((uint32_t)0x00003800) |
Referenced by RCC_GetClocksFreq().
| #define CFGR_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) |
Referenced by RCC_ADCCLKConfig().
| #define CFGR_ADCPRE_Set_Mask ((uint32_t)0x0000C000) |
Referenced by RCC_GetClocksFreq().
| #define CSR_RMVF_Set ((uint32_t)0x01000000) |
Referenced by RCC_ClearFlag().
| #define FLAG_Mask ((uint8_t)0x1F) |
Referenced by RCC_GetFlagStatus().
| #define CIR_BYTE2_ADDRESS ((uint32_t)0x40021009) |
Referenced by RCC_ITConfig().
| #define CIR_BYTE3_ADDRESS ((uint32_t)0x4002100A) |
Referenced by RCC_ClearITPendingBit().
| #define CFGR_BYTE4_ADDRESS ((uint32_t)0x40021007) |
Referenced by RCC_MCOConfig().
| #define BDCR_ADDRESS (PERIPH_BASE + BDCR_OFFSET) |
Referenced by RCC_LSEConfig().
| #define HSEStartUp_TimeOut ((uint16_t)0x0500) |