AT91x40

Register definitions. More...

Collaboration diagram for AT91x40:

Defines
#define	EBI_BASE   0xFFE00000
	EBI base address.
#define	SF_BASE   0xFFF00000
	Special function register base address.
#define	USART1_BASE   0xFFFCC000
	USART 1 base address.
#define	USART0_BASE   0xFFFD0000
	USART 0 base address.
#define	TC_BASE   0xFFFE0000
	TC base address.
#define	PIO_BASE   0xFFFF0000
	PIO base address.
#define	PS_BASE   0xFFFF4000
	PS base address.
#define	WD_BASE   0xFFFF8000
	Watch Dog register base address.
#define	AIC_BASE   0xFFFFF000
#define	PERIPH_RPR_OFF   0x00000030
	Receive pointer register offset.
#define	PERIPH_RCR_OFF   0x00000034
	Receive counter register offset.
#define	PERIPH_TPR_OFF   0x00000038
	Transmit pointer register offset.
#define	PERIPH_TCR_OFF   0x0000003C
	Transmit counter register offset.
#define	USART_HAS_PDC
Peripheral Identifiers and Interrupts
#define	FIQ_ID   0
	Fast interrupt ID.
#define	SWIRQ_ID   1
	Software interrupt ID.
#define	US0_ID   2
	USART 0 ID.
#define	US1_ID   3
	USART 1 ID.
#define	TC0_ID   4
	Timer 0 ID.
#define	TC1_ID   5
	Timer 1 ID.
#define	TC2_ID   6
	Timer 2 ID.
#define	WDI_ID   7
	Watchdog interrupt ID.
#define	PIO_ID   8
	Parallel I/O controller ID.
#define	IRQ0_ID   16
	External interrupt 0 ID.
#define	IRQ1_ID   17
	External interrupt 1 ID.
#define	IRQ2_ID   18
	External interrupt 2 ID.
USART Peripheral Multiplexing
#define	P15_RXD0   15
#define	P14_TXD0   14
#define	P13_SCK0   13
#define	P22_RXD1   22
#define	P21_TXD1   21
#define	P20_SCK1   20

---

Detailed Description

Register definitions.

---

Define Documentation

#define FIQ_ID   0

Fast interrupt ID.

#define SWIRQ_ID   1

Software interrupt ID.

#define US0_ID   2

USART 0 ID.

#define US1_ID   3

USART 1 ID.

#define TC0_ID   4

Timer 0 ID.

#define TC1_ID   5

Timer 1 ID.

#define TC2_ID   6

Timer 2 ID.

#define WDI_ID   7

Watchdog interrupt ID.

#define PIO_ID   8

Parallel I/O controller ID.

Referenced by GpioPortConfigSet().

#define IRQ0_ID   16

External interrupt 0 ID.

#define IRQ1_ID   17

External interrupt 1 ID.

#define IRQ2_ID   18

External interrupt 2 ID.

#define EBI_BASE   0xFFE00000

EBI base address.

#define SF_BASE   0xFFF00000

Special function register base address.

#define USART1_BASE   0xFFFCC000

USART 1 base address.

#define USART0_BASE   0xFFFD0000

USART 0 base address.

#define TC_BASE   0xFFFE0000

TC base address.

#define PIO_BASE   0xFFFF0000

PIO base address.

#define PS_BASE   0xFFFF4000

PS base address.

#define WD_BASE   0xFFFF8000

Watch Dog register base address.

#define AIC_BASE   0xFFFFF000

AIC base address.

#define PERIPH_RPR_OFF   0x00000030

Receive pointer register offset.

#define PERIPH_RCR_OFF   0x00000034

Receive counter register offset.

#define PERIPH_TPR_OFF   0x00000038

Transmit pointer register offset.

#define PERIPH_TCR_OFF   0x0000003C

Transmit counter register offset.

#define USART_HAS_PDC

#define P15_RXD0   15

#define P14_TXD0   14

#define P13_SCK0   13

#define P22_RXD1   22

#define P21_TXD1   21

#define P20_SCK1   20