XgNutArchArmv7mLpcSpi

SPI Control Register
#define	SPCR_OFF   0x00000000
#define	SPCR   (LPC_SPI_BASE + SPCR_OFF)
#define	SPCR_EN   (1 << 2)
#define	SPCR_CPHA   (1 << 3)
#define	SPCR_CPOL   (1 << 4)
#define	SPCR_MSTR   (1 << 5)
#define	SPCR_LSBF   (1 << 6)
#define	SPCR_SPIE   (1 << 7)
#define	SPCR_BITS_LSB   8
#define	SPCR_BITS   0x00000F00
#define	SPCR_8BITS   0x00000800
#define	SPCR_9BITS   0x00000900
#define	SPCR_10BITS   0x00000A00
#define	SPCR_11BITS   0x00000B00
#define	SPCR_12BITS   0x00000C00
#define	SPCR_13BITS   0x00000D00
#define	SPCR_14BITS   0x00000E00
#define	SPCR_15BITS   0x00000F00
#define	SPCR_16BITS   0x00000000
SPI Status Register
#define	SPSR_OFF   0x00000004
#define	SPSR   (LPC_SPI_BASE + SPSR_OFF)
#define	SPSR_ABRT   (1 << 3)
#define	SPSR_MODF   (1 << 4)
#define	SPSR_ROVR   (1 << 5)
#define	SPSR_WCOL   (1 << 6)
#define	SPSR_SPIF   (1 << 7)
SPI Data Register
#define	SPDR_OFF   0x00000008
#define	SPDR   (LPC_SPI_BASE + SPDR_OFF)
SPI Clock Counter Register
#define	SPCCR_OFF   0x0000000C
#define	SPCCR   (LPC_SPI_BASE + SPCCR_OFF)
SPI Interrupt Flag Register
#define	SPINT_OFF   0x0000001C
#define	SPINT   (LPC_SPI_BASE + SPINT_OFF)
#define	SPINT_SPIF   (1 << 0)

---

Define Documentation

#define SPCR_OFF   0x00000000

#define SPCR   (LPC_SPI_BASE + SPCR_OFF)

Referenced by AvrSpiBus0Select(), AvrSpiBus0Transfer(), SpiFlashEnable(), Sppi0Enable(), and VsPlayerInit().

#define SPCR_EN   (1 << 2)

#define SPCR_CPHA   (1 << 3)

#define SPCR_CPOL   (1 << 4)

#define SPCR_MSTR   (1 << 5)

#define SPCR_LSBF   (1 << 6)

#define SPCR_SPIE   (1 << 7)

#define SPCR_BITS_LSB   8

#define SPCR_BITS   0x00000F00

#define SPCR_8BITS   0x00000800

#define SPCR_9BITS   0x00000900

#define SPCR_10BITS   0x00000A00

#define SPCR_11BITS   0x00000B00

#define SPCR_12BITS   0x00000C00

#define SPCR_13BITS   0x00000D00

#define SPCR_14BITS   0x00000E00

#define SPCR_15BITS   0x00000F00

#define SPCR_16BITS   0x00000000

#define SPSR_OFF   0x00000004

#define SPSR   (LPC_SPI_BASE + SPSR_OFF)

Referenced by AvrSpiBus0Select(), AvrSpiBus0Transfer(), Sppi0Byte(), Sppi0Enable(), and VsPlayerInit().

#define SPSR_ABRT   (1 << 3)

#define SPSR_MODF   (1 << 4)

#define SPSR_ROVR   (1 << 5)

#define SPSR_WCOL   (1 << 6)

#define SPSR_SPIF   (1 << 7)

#define SPDR_OFF   0x00000008

#define SPDR   (LPC_SPI_BASE + SPDR_OFF)

Referenced by AvrSpiBus0Select(), AvrSpiBus0Transfer(), Sppi0Byte(), Sppi0Enable(), and VsPlayerInit().

#define SPCCR_OFF   0x0000000C

#define SPCCR   (LPC_SPI_BASE + SPCCR_OFF)

#define SPINT_OFF   0x0000001C

#define SPINT   (LPC_SPI_BASE + SPINT_OFF)

#define SPINT_SPIF   (1 << 0)