Defines | |
| #define | TX_GPIO_PORT NUTGPIO_PORT0 |
| Debug UART0 GPIO configuartion and assignment. | |
| #define | TX_GPIO_PIN 2 |
| #define | TX_GPIO_PIN_CFG GPIO_CFG_OUTPUT | GPIO_CFG_PERIPHERAL1 |
| #define | RX_GPIO_PORT NUTGPIO_PORT0 |
| #define | RX_GPIO_PIN 3 |
| #define | RX_GPIO_PIN_CFG GPIO_CFG_INPUT | GPIO_CFG_PERIPHERAL1 |
| #define | USARTn LPC_UART0 |
| Debug UART0 base configuration. | |
| #define | USARTnBase LPC_UART0_BASE |
| #define | TX_GPIO_PORT NUTGPIO_PORT0 |
| USART1 GPIO configuartion and assignment. | |
| #define | TX_GPIO_PIN 15 |
| #define | TX_GPIO_PIN_CFG GPIO_CFG_OUTPUT | GPIO_CFG_PERIPHERAL1 |
| #define | RX_GPIO_PORT NUTGPIO_PORT0 |
| #define | RX_GPIO_PIN 16 |
| #define | RX_GPIO_PIN_CFG GPIO_CFG_INPUT | GPIO_CFG_PERIPHERAL1 |
| #define | USARTn LPC_UART1 |
| Debug UART1 base configuration. | |
| #define | USARTnBase LPC_UART1_BASE |
| #define | TX_GPIO_PORT NUTGPIO_PORT0 |
| USART2 GPIO configuartion and assignment. | |
| #define | TX_GPIO_PIN 10 |
| #define | TX_GPIO_PIN_CFG GPIO_CFG_OUTPUT | GPIO_CFG_PERIPHERAL1 |
| #define | RX_GPIO_PORT NUTGPIO_PORT0 |
| #define | RX_GPIO_PIN 11 |
| #define | RX_GPIO_PIN_CFG GPIO_CFG_INPUT | GPIO_CFG_PERIPHERAL1 |
| #define | USARTn LPC_UART2 |
| Debug UART2 base configuration. | |
| #define | USARTnBase LPC_UART2_BASE |
| #define | TX_GPIO_PORT NUTGPIO_PORT0 |
| USART3 GPIO configuartion and assignment. | |
| #define | TX_GPIO_PIN 26 |
| #define | TX_GPIO_PIN_CFG GPIO_CFG_OUTPUT | GPIO_CFG_PERIPHERAL3 |
| #define | RX_GPIO_PORT NUTGPIO_PORT0 |
| #define | RX_GPIO_PIN 27 |
| #define | RX_GPIO_PIN_CFG GPIO_CFG_INPUT | GPIO_CFG_PERIPHERAL3 |
| #define | USARTn LPC_UART3 |
| Debug UART3 base configuration. | |
| #define | USARTnBase LPC_UART3_BASE |
LPC17xx USART0 Device | |
| NUTDEVICE | devDebug0 |
| Debug UART 0 device information structure. | |
LPC17xx USART1 Device | |
| NUTDEVICE | devDebug1 |
| Debug UART 1 device information structure. | |
LPC17xx USART2 Device | |
| NUTDEVICE | devDebug2 |
| Debug UART 2 device information structure. | |
LPC17xx USART3 Device | |
| NUTDEVICE | devDebug3 |
| Debug UART 3 device information structure. | |
| #define TX_GPIO_PORT NUTGPIO_PORT0 |
Debug UART0 GPIO configuartion and assignment.
| #define TX_GPIO_PIN 2 |
| #define TX_GPIO_PIN_CFG GPIO_CFG_OUTPUT | GPIO_CFG_PERIPHERAL1 |
| #define RX_GPIO_PORT NUTGPIO_PORT0 |
| #define RX_GPIO_PIN 3 |
| #define RX_GPIO_PIN_CFG GPIO_CFG_INPUT | GPIO_CFG_PERIPHERAL1 |
| #define USARTn LPC_UART0 |
Debug UART0 base configuration.
| #define USARTnBase LPC_UART0_BASE |
| #define TX_GPIO_PORT NUTGPIO_PORT0 |
USART1 GPIO configuartion and assignment.
| #define TX_GPIO_PIN 15 |
| #define TX_GPIO_PIN_CFG GPIO_CFG_OUTPUT | GPIO_CFG_PERIPHERAL1 |
| #define RX_GPIO_PORT NUTGPIO_PORT0 |
| #define RX_GPIO_PIN 16 |
| #define RX_GPIO_PIN_CFG GPIO_CFG_INPUT | GPIO_CFG_PERIPHERAL1 |
| #define USARTn LPC_UART1 |
Debug UART1 base configuration.
| #define USARTnBase LPC_UART1_BASE |
| #define TX_GPIO_PORT NUTGPIO_PORT0 |
USART2 GPIO configuartion and assignment.
| #define TX_GPIO_PIN 10 |
| #define TX_GPIO_PIN_CFG GPIO_CFG_OUTPUT | GPIO_CFG_PERIPHERAL1 |
| #define RX_GPIO_PORT NUTGPIO_PORT0 |
| #define RX_GPIO_PIN 11 |
| #define RX_GPIO_PIN_CFG GPIO_CFG_INPUT | GPIO_CFG_PERIPHERAL1 |
| #define USARTn LPC_UART2 |
Debug UART2 base configuration.
| #define USARTnBase LPC_UART2_BASE |
| #define TX_GPIO_PORT NUTGPIO_PORT0 |
USART3 GPIO configuartion and assignment.
| #define TX_GPIO_PIN 26 |
| #define TX_GPIO_PIN_CFG GPIO_CFG_OUTPUT | GPIO_CFG_PERIPHERAL3 |
| #define RX_GPIO_PORT NUTGPIO_PORT0 |
| #define RX_GPIO_PIN 27 |
| #define RX_GPIO_PIN_CFG GPIO_CFG_INPUT | GPIO_CFG_PERIPHERAL3 |
| #define USARTn LPC_UART3 |
Debug UART3 base configuration.
| #define USARTnBase LPC_UART3_BASE |
{
NULL,
{'u', 'a', 'r', 't', '0', 0, 0, 0, 0}
,
0,
LPC_UART0_BASE,
0,
NULL,
&dbg0file,
Lpc17xxDevDebugInit,
Lpc17xxDevDebugIOCtl,
NULL,
Lpc17xxDevDebugWrite,
Lpc17xxDevDebugOpen,
Lpc17xxDevDebugClose,
NULL
}
Debug UART 0 device information structure.
Debug device 0 information structure.
An application must pass a pointer to this structure to NutRegisterDevice() before using the serial communication driver of the LPC17xx's on-chip USART0.
The device is named usart0.
{
NULL,
{'u', 'a', 'r', 't', '1', 0, 0, 0, 0}
,
0,
LPC_UART1_BASE,
0,
NULL,
&dbg1file,
Lpc17xxDevDebugInit,
Lpc17xxDevDebugIOCtl,
NULL,
Lpc17xxDevDebugWrite,
Lpc17xxDevDebugOpen,
Lpc17xxDevDebugClose,
NULL
}
Debug UART 1 device information structure.
Debug device 1 information structure.
An application must pass a pointer to this structure to NutRegisterDevice() before using the serial communication driver of the LPC17xx's on-chip USART1.
The device is named usart1.
{
NULL,
{'u', 'a', 'r', 't', '2', 0, 0, 0, 0}
,
0,
LPC_UART2_BASE,
0,
NULL,
&dbg2file,
Lpc17xxDevDebugInit,
Lpc17xxDevDebugIOCtl,
NULL,
Lpc17xxDevDebugWrite,
Lpc17xxDevDebugOpen,
Lpc17xxDevDebugClose,
NULL
}
Debug UART 2 device information structure.
An application must pass a pointer to this structure to NutRegisterDevice() before using the serial communication driver of the LPC17xx's on-chip USART2.
The device is named usart2.
{
NULL,
{'u', 'a', 'r', 't', '3', 0, 0, 0, 0}
,
0,
LPC_UART3_BASE,
0,
NULL,
&dbg3file,
Lpc17xxDevDebugInit,
Lpc17xxDevDebugIOCtl,
NULL,
Lpc17xxDevDebugWrite,
Lpc17xxDevDebugOpen,
Lpc17xxDevDebugClose,
NULL
}
Debug UART 3 device information structure.
An application must pass a pointer to this structure to NutRegisterDevice() before using the serial communication driver of the LPC17xx's on-chip USART3.
The device is named usart3.