LPC UART definitions. More...
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UART Receiver Buffer Registers | |
| #define | UART_RBR_OFF 0x00000000 |
UART Transmit Holding Registers | |
| #define | UART_THR_OFF 0x00000000 |
UART Divisor Latch LSB Registers | |
| #define | UART_DLL_OFF 0x00000000 |
UART Divisor Latch MSB Registers | |
| #define | UART_DLM_OFF 0x00000004 |
UART Interrupt Enable Registers | |
| #define | UART_IER_OFF 0x00000004 |
| #define | UART_INT_RDA (1 << 0) |
| #define | UART_INT_THRE (1 << 1) |
| #define | UART_INT_RLS (1 << 2) |
| #define | UART_INT_ABEO (1 << 8) |
| #define | UART_INT_ABTO (1 << 9) |
UART Interrupt Identification Registers | |
| #define | UART_IIR_OFF 0x00000008 |
| #define | UART_INT_STATUS (1 << 0) |
| #define | UART_INT_ID 0x0000000E |
| #define | UART_INT_ID_RLS 0x00000006 |
| #define | UART_INT_ID_RDA 0x00000004 |
| #define | UART_INT_ID_CTI 0x0000000C |
| #define | UART_INT_ID_THRE 0x00000002 |
| #define | UART_INT_FIFO 0x000000C0 |
UART FIFO Control Registers | |
| #define | UART_FCR_OFF 0x00000008 |
| #define | UART_FIFO_EN (1 << 0) |
| #define | UART_FIFO_RXRST (1 << 1) |
| #define | UART_FIFO_TXRST (1 << 2) |
| #define | UART_FIFO_DMA (1 << 3) |
| #define | UART_FIFO_RXTRIG 0x000000C0 |
| #define | UART_FIFO_RXTRIG_LSB 6 |
UART Line Control Registers | |
| #define | UART_LCR_OFF 0x0000000C |
| #define | UART_WLEN 0x00000003 |
| #define | UART_WLEN_5 0x00000000 |
| #define | UART_WLEN_6 0x00000001 |
| #define | UART_WLEN_7 0x00000002 |
| #define | UART_WLEN_8 0x00000003 |
| #define | UART_STOP_2 (1 << 2) |
| #define | UART_PAR 0x00000038 |
| #define | UART_PAR_NONE 0x00000000 |
| #define | UART_PAR_ODD 0x00000008 |
| Odd parity. | |
| #define | UART_PAR_EVEN 0x00000018 |
| Even parity. | |
| #define | UART_PAR_MARK 0x00000028 |
| Marked parity. | |
| #define | UART_PAR_SPACE 0x00000038 |
| Space parity. | |
| #define | UART_BREAK (1 << 6) |
| #define | UART_DLAB (1 << 7) |
UART Line Status Registers | |
| #define | UART_LSR_OFF 0x00000014 |
| #define | UART_RDR (1 << 0) |
| #define | UART_OE (1 << 1) |
| #define | UART_PE (1 << 2) |
| #define | UART_FE (1 << 3) |
| #define | UART_BI (1 << 4) |
| #define | UART_THRE (1 << 5) |
| #define | UART_TEMT (1 << 6) |
| #define | UART_RXFE (1 << 7) |
UART Scratch Pad Registers | |
| #define | UART_SCR_OFF 0x0000001C |
UART Auto-Baud Control Registers | |
| #define | UART_ACR_OFF 0x00000020 |
| #define | UART_AB_START (1 << 0) |
| #define | UART_AB_MODE (1 << 1) |
| #define | UART_AB_AUTORESTART (1 << 2) |
UART IrDA Control Registers | |
| #define | UART_ICR_OFF 0x00000024 |
| #define | UART_IRDA_EN (1 << 0) |
| #define | UART_IRDA_INV (1 << 1) |
| #define | UART_PULSE 0x0000003C |
| #define | UART_PULSE_VAR 0x00000000 |
| #define | UART_PULSE_2PCLK 0x00000004 |
| #define | UART_PULSE_4PCLK 0x0000000C |
| #define | UART_PULSE_8PCLK 0x00000014 |
| #define | UART_PULSE_16PCLK 0x0000001C |
| #define | UART_PULSE_32PCLK 0x00000024 |
| #define | UART_PULSE_64PCLK 0x0000002C |
| #define | UART_PULSE_128PCLK 0x00000034 |
| #define | UART_PULSE_256PCLK 0x0000003C |
UART Fractional Divider Registers | |
| #define | UART_FDR_OFF 0x00000028 |
| #define | UART_DIVADDVAL 0x0000000F |
| #define | UART_DIVADDVAL_LSB 0 |
| #define | UART_MULVAL 0x000000F0 |
| #define | UART_MULVAL_LSB 4 |
UART Transmit Enable Registers | |
| #define | UART_TER_OFF 0x00000030 |
| #define | UART_TXEN (1 << 7) |
LPC UART definitions.
* $Id$ *