This file provides firmware functions to manage the following functionalities of the Reset and clock control (RCC) peripheral: More...

#include <arch/cm3.h>
#include "arch/cm3/stm/stm32l1xx_rcc.h"
#include <sys/nutdebug.h>
#include <stdlib.h>
#include <errno.h>

Include dependency graph for stm32l1xx_rcc.c:

Defines
#define	assert_param NUTASSERT
#define	RCC_OFFSET (RCC_BASE - PERIPH_BASE)
#define	CR_OFFSET (RCC_OFFSET + 0x00)
#define	HSION_BitNumber 0x00
#define	CR_HSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
#define	MSION_BitNumber 0x08
#define	CR_MSION_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))
#define	PLLON_BitNumber 0x18
#define	CR_PLLON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
#define	CSSON_BitNumber 0x1C
#define	CR_CSSON_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
#define	CSR_OFFSET (RCC_OFFSET + 0x34)
#define	LSION_BitNumber 0x00
#define	CSR_LSION_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
#define	RTCEN_BitNumber 0x16
#define	CSR_RTCEN_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))
#define	RTCRST_BitNumber 0x17
#define	CSR_RTCRST_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))
#define	FLAG_MASK ((uint8_t)0x1F)
#define	CR_BYTE3_ADDRESS ((uint32_t)0x40023802)
#define	ICSCR_BYTE4_ADDRESS ((uint32_t)0x40023807)
#define	CFGR_BYTE3_ADDRESS ((uint32_t)0x4002380A)
#define	CFGR_BYTE4_ADDRESS ((uint32_t)0x4002380B)
#define	CIR_BYTE2_ADDRESS ((uint32_t)0x4002380D)
#define	CIR_BYTE3_ADDRESS ((uint32_t)0x4002380E)
#define	CSR_BYTE2_ADDRESS ((uint32_t)0x40023835)
Functions
void	RCC_DeInit (void)
	Resets the RCC clock configuration to the default reset state.
void	RCC_HSEConfig (uint8_t RCC_HSE)
	Configures the External High Speed oscillator (HSE).
ErrorStatus	RCC_WaitForHSEStartUp (void)
	Waits for HSE start-up.
void	RCC_AdjustMSICalibrationValue (uint8_t MSICalibrationValue)
	Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
void	RCC_MSIRangeConfig (uint32_t RCC_MSIRange)
	Configures the Internal Multi Speed oscillator (MSI) clock range.
void	RCC_MSICmd (FunctionalState NewState)
	Enables or disables the Internal Multi Speed oscillator (MSI).
void	RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
	Adjusts the Internal High Speed oscillator (HSI) calibration value.
void	RCC_HSICmd (FunctionalState NewState)
	Enables or disables the Internal High Speed oscillator (HSI).
void	RCC_LSEConfig (uint8_t RCC_LSE)
	Configures the External Low Speed oscillator (LSE).
void	RCC_LSICmd (FunctionalState NewState)
	Enables or disables the Internal Low Speed oscillator (LSI).
void	RCC_PLLConfig (uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)
	Configures the PLL clock source and multiplication factor.
void	RCC_PLLCmd (FunctionalState NewState)
	Enables or disables the main PLL.
void	RCC_ClockSecuritySystemCmd (FunctionalState NewState)
	Enables or disables the Clock Security System.
void	RCC_MCOConfig (uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)
	Selects the clock source to output on MCO pin (PA8).
void	RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
	Configures the system clock (SYSCLK).
uint8_t	RCC_GetSYSCLKSource (void)
	Returns the clock source used as system clock.
void	RCC_HCLKConfig (uint32_t RCC_SYSCLK)
	Configures the AHB clock (HCLK).
void	RCC_PCLK1Config (uint32_t RCC_HCLK)
	Configures the Low Speed APB clock (PCLK1).
void	RCC_PCLK2Config (uint32_t RCC_HCLK)
	Configures the High Speed APB clock (PCLK2).
void	RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks)
	Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.
void	RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
	Configures the RTC clock (RTCCLK).
void	RCC_RTCCLKCmd (FunctionalState NewState)
	Enables or disables the RTC clock.
void	RCC_RTCResetCmd (FunctionalState NewState)
	Forces or releases the RTC peripheral and associated resources reset.
void	RCC_AHBPeriphClockCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
	Enables or disables the AHB peripheral clock.
void	RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
	Enables or disables the High Speed APB (APB2) peripheral clock.
void	RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
	Enables or disables the Low Speed APB (APB1) peripheral clock.
void	RCC_AHBPeriphResetCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
	Forces or releases AHB peripheral reset.
void	RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
	Forces or releases High Speed APB (APB2) peripheral reset.
void	RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
	Forces or releases Low Speed APB (APB1) peripheral reset.
void	RCC_AHBPeriphClockLPModeCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
	Enables or disables the AHB peripheral clock during SLEEP mode.
void	RCC_APB2PeriphClockLPModeCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
	Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
void	RCC_APB1PeriphClockLPModeCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
	Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
void	RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState)
	Enables or disables the specified RCC interrupts.
FlagStatus	RCC_GetFlagStatus (uint8_t RCC_FLAG)
	Checks whether the specified RCC flag is set or not.
void	RCC_ClearFlag (void)
	Clears the RCC reset flags. The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.
ITStatus	RCC_GetITStatus (uint8_t RCC_IT)
	Checks whether the specified RCC interrupt has occurred or not.
void	RCC_ClearITPendingBit (uint8_t RCC_IT)
	Clears the RCC's interrupt pending bits.

Detailed Description

This file provides firmware functions to manage the following functionalities of the Reset and clock control (RCC) peripheral:

Author:: MCD Application Team

Version:: V1.0.0

Date:

31-December-2010

Internal/external clocks, PLL, CSS and MCO configuration
System, AHB and APB busses clocks configuration
Peripheral clocks configuration
Interrupts and flags management

  *
  *          ===================================================================
  *                               RCC specific features
  *          ===================================================================
  *
  *          After reset the device is running from MSI (2 MHz) with Flash 0 WS,
  *          all peripherals are off except internal SRAM, Flash and JTAG.
  *           - There is no prescaler on High speed (AHB) and Low speed (APB) busses;
  *             all peripherals mapped on these busses are running at MSI speed.
  *           - The clock for all peripherals is switched off, except the SRAM and FLASH.
  *           - All GPIOs are in input floating state, except the JTAG pins which
  *             are assigned to be used for debug purpose.
  *
  *          Once the device started from reset, the user application has to:
  *           - Configure the clock source to be used to drive the System clock
  *             (if the application needs higher frequency/performance)
  *           - Configure the System clock frequency and Flash settings
  *           - Configure the AHB and APB busses prescalers
  *           - Enable the clock for the peripheral(s) to be used
  *           - Configure the clock source(s) for peripherals whose clocks are not
  *             derived from the System clock (ADC, RTC/LCD and IWDG)
  *
  *

Attention:

THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

Define Documentation

#define assert_param NUTASSERT

Referenced by RCC_AdjustMSICalibrationValue(), RCC_AHBPeriphClockCmd(), RCC_AHBPeriphClockLPModeCmd(), RCC_AHBPeriphResetCmd(), RCC_MCOConfig(), RCC_MSICmd(), RCC_MSIRangeConfig(), RCC_PLLConfig(), and RCC_RTCResetCmd().

Defines

Functions

Detailed Description

© COPYRIGHT 2010 STMicroelectronics

Define Documentation