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Nut/OS
4.10.3
API Reference
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Nut/OS
4.10.3
API Reference
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100 MBit Ethernet controller. More...
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Data Structures | |
| struct | _NICINFO |
| Network interface controller information structure. More... | |
Defines | |
| #define | LAN91_BASE_ADDR 0xC000 |
| #define | LAN91_BSR (LAN91_BASE_ADDR + 0x0E) |
| Bank select register. | |
| #define | LAN91_TCR (LAN91_BASE_ADDR + 0x00) |
| Bank 0 - Transmit control register. | |
| #define | LAN91_TCR_SWFDUP 0x8000 |
| #define | LAN91_TCR_EPH_LOOP 0x2000 |
| #define | LAN91_TCR_STP_SQET 0x1000 |
| #define | LAN91_TCR_FDUPLX 0x0800 |
| #define | LAN91_TCR_MON_CSN 0x0400 |
| #define | LAN91_TCR_NOCRC 0x0100 |
| #define | LAN91_TCR_PAD_EN 0x0080 |
| #define | LAN91_TCR_FORCOL 0x0004 |
| #define | LAN91_TCR_LOOP 0x0002 |
| #define | LAN91_TCR_TXENA 0x0001 |
| #define | LAN91_EPHSR (LAN91_BASE_ADDR + 0x02) |
| Bank 0 - EPH status register. | |
| #define | LAN91_RCR (LAN91_BASE_ADDR + 0x04) |
| Bank 0 - Receive control register. | |
| #define | LAN91_RCR_SOFT_RST 0x8000 |
| #define | LAN91_RCR_FILT_CAR 0x4000 |
| #define | LAN91_RCR_ABORT_ENB 0x2000 |
| #define | LAN91_RCR_STRIP_CRC 0x0200 |
| #define | LAN91_RCR_RXEN 0x0100 |
| #define | LAN91_RCR_ALMUL 0x0004 |
| #define | LAN91_RCR_PRMS 0x0002 |
| #define | LAN91_RCR_RX_ABORT 0x0001 |
| #define | LAN91_ECR (LAN91_BASE_ADDR + 0x06) |
| Bank 0 - Counter register. | |
| #define | LAN91_MIR (LAN91_BASE_ADDR + 0x08) |
| Bank 0 - Memory information register. | |
| #define | LAN91_RPCR (LAN91_BASE_ADDR + 0x0A) |
| Bank 0 - Receive / PHY control register. | |
| #define | LAN91_RPCR_SPEED 0x2000 |
| #define | LAN91_RPCR_DPLX 0x1000 |
| #define | LAN91_RPCR_ANEG 0x0800 |
| #define | LAN91_RPCR_LEDA_PAT 0x0000 |
| #define | LAN91_RPCR_LEDB_PAT 0x0010 |
| #define | LAN91_CR (LAN91_BASE_ADDR + 0x00) |
| Bank 1 - Configuration register. | |
| #define | LAN91_CR_EPH_EN 0x8000 |
| #define | LAN91_BAR (LAN91_BASE_ADDR + 0x02) |
| Bank 1 - Base address register. | |
| #define | LAN91_IAR (LAN91_BASE_ADDR + 0x04) |
| Bank 1 - Individual address register. | |
| #define | LAN91_GPR (LAN91_BASE_ADDR + 0x0A) |
| Bank 1 - General purpose register. | |
| #define | LAN91_CTR (LAN91_BASE_ADDR + 0x0C) |
| Bank 1 - Control register. | |
| #define | LAN91_CTR_RCV_BAD 0x4000 |
| #define | LAN91_CTR_AUTO_RELEASE 0x0800 |
| #define | LAN91_MMUCR (LAN91_BASE_ADDR + 0x00) |
| Bank 2 - MMU command register. | |
| #define | LAN91_MMUCR_BUSY 0x0001 |
| #define | LAN91_MMU_NOP 0 |
| #define | LAN91_MMU_ALO (1<<5) |
| #define | LAN91_MMU_RST (2<<5) |
| #define | LAN91_MMU_REM (3<<5) |
| #define | LAN91_MMU_TOP (4<<5) |
| #define | LAN91_MMU_PKT (5<<5) |
| #define | LAN91_MMU_ENQ (6<<5) |
| #define | LAN91_MMU_RTX (7<<5) |
| #define | LAN91_PNR (LAN91_BASE_ADDR + 0x02) |
| Bank 2 - Packet number register. | |
| #define | LAN91_ARR (LAN91_BASE_ADDR + 0x03) |
| Bank 2 - Allocation result register. | |
| #define | LAN91_ARR_FAILED 0x80 |
| #define | LAN91_FIFO (LAN91_BASE_ADDR + 0x04) |
| Bank 2 - FIFO ports register. | |
| #define | LAN91_PTR (LAN91_BASE_ADDR + 0x06) |
| Bank 2 - Pointer register. | |
| #define | LAN91_PTR_RCV 0x8000 |
| #define | LAN91_PTR_AUTO_INCR 0x4000 |
| #define | LAN91_PTR_READ 0x2000 |
| #define | LAN91_PTR_ETEN 0x1000 |
| #define | LAN91_PTR_NOT_EMPTY 0x0800 |
| #define | LAN91_DATA (LAN91_BASE_ADDR + 0x08) |
| Bank 2 - Data register. | |
| #define | LAN91_IST (LAN91_BASE_ADDR + 0x0C) |
| Bank 2 - Interrupt status register. | |
| #define | LAN91_ACK (LAN91_BASE_ADDR + 0x0C) |
| Bank 2 - Interrupt acknowledge register. | |
| #define | LAN91_MSK (LAN91_BASE_ADDR + 0x0D) |
| Bank 2 - Interrupt mask register. | |
| #define | LAN91_INT_MD 0x80 |
| PHY state change interrupt bit mask. | |
| #define | LAN91_INT_ERCV 0x40 |
| Early receive interrupt bit mask. | |
| #define | LAN91_INT_EPH 0x20 |
| Ethernet protocol interrupt bit mask. | |
| #define | LAN91_INT_RX_OVRN 0x10 |
| Receive overrun interrupt bit mask. | |
| #define | LAN91_INT_ALLOC 0x08 |
| Transmit allocation interrupt bit mask. | |
| #define | LAN91_INT_TX_EMPTY 0x04 |
| Transmitter empty interrupt bit mask. | |
| #define | LAN91_INT_TX 0x02 |
| Transmit complete interrupt bit mask. | |
| #define | LAN91_INT_RCV 0x01 |
| Receive interrupt bit mask. | |
| #define | LAN91_MT (LAN91_BASE_ADDR + 0x00) |
| Bank 3 - Multicast table register. | |
| #define | LAN91_MGMT (LAN91_BASE_ADDR + 0x08) |
| Bank 3 - Management interface register. | |
| #define | LAN91_MGMT_MDOE 0x08 |
| #define | LAN91_MGMT_MCLK 0x04 |
| #define | LAN91_MGMT_MDI 0x02 |
| #define | LAN91_MGMT_MDO 0x01 |
| #define | LAN91_REV (LAN91_BASE_ADDR + 0x0A) |
| Bank 3 - Revision register. | |
| #define | LAN91_ERCV (LAN91_BASE_ADDR + 0x0C) |
| Bank 3 - Early RCV register. | |
| #define | LAN91_PHYCR 0 |
| PHY control register. | |
| #define | LAN91_PHYCR_RST 0x8000 |
| #define | LAN91_PHYCR_LPBK 0x4000 |
| #define | LAN91_PHYCR_SPEED 0x2000 |
| #define | LAN91_PHYCR_ANEG_EN 0x1000 |
| #define | LAN91_PHYCR_PDN 0x0800 |
| #define | LAN91_PHYCR_MII_DIS 0x0400 |
| #define | LAN91_PHYCR_ANEG_RST 0x0200 |
| #define | LAN91_PHYCR_DPLX 0x0100 |
| #define | LAN91_PHYCR_COLST 0x0080 |
| #define | LAN91_PHYSR 1 |
| PHY status register. | |
| #define | LAN91_PHYSR_CAP_T4 0x8000 |
| #define | LAN91_PHYSR_CAP_TXF 0x4000 |
| #define | LAN91_PHYSR_CAP_TXH 0x2000 |
| #define | LAN91_PHYSR_CAP_TF 0x1000 |
| #define | LAN91_PHYSR_CAP_TH 0x0800 |
| #define | LAN91_PHYSR_CAP_SUPR 0x0040 |
| #define | LAN91_PHYSR_ANEG_ACK 0x0020 |
| #define | LAN91_PHYSR_REM_FLT 0x0010 |
| #define | LAN91_PHYSR_CAP_ANEG 0x0008 |
| #define | LAN91_PHYSR_LINK 0x0004 |
| #define | LAN91_PHYSR_JAB 0x0002 |
| #define | LAN91_PHYSR_EXREG 0x0001 |
| #define | LAN91_PHYID1 2 |
| PHY identifier register 1. | |
| #define | LAN91_PHYID2 3 |
| PHY identifier register 1. | |
| #define | LAN91_PHYANAD 4 |
| PHY auto-negotiation advertisement register. | |
| #define | LAN91_PHYANAD_NP 0x8000 |
| #define | LAN91_PHYANAD_ACK 0x4000 |
| #define | LAN91_PHYANAD_RF 0x2000 |
| #define | LAN91_PHYANAD_T4 0x0200 |
| #define | LAN91_PHYANAD_TX_FDX 0x0100 |
| #define | LAN91_PHYANAD_TX_HDX 0x0080 |
| #define | LAN91_PHYANAD_10FDX 0x0040 |
| #define | LAN91_PHYANAD_10_HDX 0x0020 |
| #define | LAN91_PHYANAD_CSMA 0x0001 |
| #define | LAN91_PHYANRC 5 |
| PHY auto-negotiation remote end capability register. | |
| #define | LAN91_PHYCFR1 16 |
| PHY configuration register 1. | |
| #define | LAN91_PHYCFR2 17 |
| PHY configuration register 2. | |
| #define | LAN91_PHYSOR 18 |
| PHY status output register. | |
| #define | LAN91_PHYSOR_INT 0x8000 |
| #define | LAN91_PHYSOR_LNKFAIL 0x4000 |
| #define | LAN91_PHYSOR_LOSSSYNC 0x2000 |
| #define | LAN91_PHYSOR_CWRD 0x1000 |
| #define | LAN91_PHYSOR_SSD 0x0800 |
| #define | LAN91_PHYSOR_ESD 0x0400 |
| #define | LAN91_PHYSOR_RPOL 0x0200 |
| #define | LAN91_PHYSOR_JAB 0x0100 |
| #define | LAN91_PHYSOR_SPDDET 0x0080 |
| #define | LAN91_PHYSOR_DPLXDET 0x0040 |
| #define | LAN91_PHYMSK 19 |
| PHY mask register. | |
| #define | LAN91_PHYMSK_MINT 0x8000 |
| #define | LAN91_PHYMSK_MLNKFAIL 0x4000 |
| #define | LAN91_PHYMSK_MLOSSSYN 0x2000 |
| #define | LAN91_PHYMSK_MCWRD 0x1000 |
| #define | LAN91_PHYMSK_MSSD 0x0800 |
| #define | LAN91_PHYMSK_MESD 0x0400 |
| #define | LAN91_PHYMSK_MRPOL 0x0200 |
| #define | LAN91_PHYMSK_MJAB 0x0100 |
| #define | LAN91_PHYMSK_MSPDDT 0x0080 |
| #define | LAN91_PHYMSK_MDPLDT 0x0040 |
| #define | nic_outlb(addr, val) (*(volatile uint8_t *)(addr) = (val)) |
| #define | nic_outhb(addr, val) (*(volatile uint8_t *)((addr) + 1) = (val)) |
| #define | nic_outwx(addr, val) (*(volatile uint16_t *)(addr) = (val)) |
| #define | nic_outw(addr, val) |
| #define | nic_inlb(addr) (*(volatile uint8_t *)(addr)) |
| #define | nic_inhb(addr) (*(volatile uint8_t *)((addr) + 1)) |
| #define | nic_inw(addr) (*(volatile uint16_t *)(addr)) |
| #define | nic_bs(bank) nic_outlb(LAN91_BSR, bank) |
Typedefs | |
| typedef struct _NICINFO | NICINFO |
| Network interface controller information type. | |
Functions | |
| void | NicRxLanc (void *arg) |
Variables | |
| NUTDEVICE | devLan91 |
| Device information structure. | |
100 MBit Ethernet controller.
| #define LAN91_BSR (LAN91_BASE_ADDR + 0x0E) |
| #define LAN91_TCR (LAN91_BASE_ADDR + 0x00) |
| #define LAN91_TCR_SWFDUP 0x8000 |
| #define LAN91_TCR_EPH_LOOP 0x2000 |
| #define LAN91_TCR_STP_SQET 0x1000 |
| #define LAN91_TCR_FDUPLX 0x0800 |
| #define LAN91_TCR_MON_CSN 0x0400 |
| #define LAN91_TCR_NOCRC 0x0100 |
| #define LAN91_TCR_PAD_EN 0x0080 |
| #define LAN91_TCR_FORCOL 0x0004 |
| #define LAN91_TCR_LOOP 0x0002 |
| #define LAN91_TCR_TXENA 0x0001 |
| #define LAN91_EPHSR (LAN91_BASE_ADDR + 0x02) |
| #define LAN91_RCR (LAN91_BASE_ADDR + 0x04) |
| #define LAN91_RCR_SOFT_RST 0x8000 |
| #define LAN91_RCR_FILT_CAR 0x4000 |
| #define LAN91_RCR_ABORT_ENB 0x2000 |
| #define LAN91_RCR_STRIP_CRC 0x0200 |
| #define LAN91_RCR_RXEN 0x0100 |
| #define LAN91_RCR_ALMUL 0x0004 |
| #define LAN91_RCR_PRMS 0x0002 |
| #define LAN91_RCR_RX_ABORT 0x0001 |
| #define LAN91_ECR (LAN91_BASE_ADDR + 0x06) |
| #define LAN91_MIR (LAN91_BASE_ADDR + 0x08) |
| #define LAN91_RPCR (LAN91_BASE_ADDR + 0x0A) |
| #define LAN91_RPCR_SPEED 0x2000 |
LAN91_RPCR bit mask, PHY operates at 100 Mbps.
| #define LAN91_RPCR_DPLX 0x1000 |
LAN91_RPCR bit mask, PHY operates at full duplex mode.
| #define LAN91_RPCR_ANEG 0x0800 |
LAN91_RPCR bit mask, sets PHY in auto-negotiation mode.
| #define LAN91_RPCR_LEDA_PAT 0x0000 |
LAN91_RPCR bit mask for LEDA mode.
| #define LAN91_RPCR_LEDB_PAT 0x0010 |
LAN91_RPCR bit mask for LEDB mode.
| #define LAN91_CR (LAN91_BASE_ADDR + 0x00) |
| #define LAN91_BAR (LAN91_BASE_ADDR + 0x02) |
| #define LAN91_IAR (LAN91_BASE_ADDR + 0x04) |
| #define LAN91_GPR (LAN91_BASE_ADDR + 0x0A) |
| #define LAN91_CTR (LAN91_BASE_ADDR + 0x0C) |
| #define LAN91_CTR_AUTO_RELEASE 0x0800 |
| #define LAN91_MMUCR (LAN91_BASE_ADDR + 0x00) |
| #define LAN91_PNR (LAN91_BASE_ADDR + 0x02) |
| #define LAN91_ARR (LAN91_BASE_ADDR + 0x03) |
| #define LAN91_FIFO (LAN91_BASE_ADDR + 0x04) |
| #define LAN91_PTR (LAN91_BASE_ADDR + 0x06) |
| #define LAN91_DATA (LAN91_BASE_ADDR + 0x08) |
| #define LAN91_IST (LAN91_BASE_ADDR + 0x0C) |
| #define LAN91_ACK (LAN91_BASE_ADDR + 0x0C) |
| #define LAN91_MSK (LAN91_BASE_ADDR + 0x0D) |
Bank 2 - Interrupt mask register.
Definition at line 218 of file lan91.h.
Referenced by NicRxLanc().
| #define LAN91_INT_MD 0x80 |
| #define LAN91_INT_ERCV 0x40 |
| #define LAN91_INT_EPH 0x20 |
| #define LAN91_INT_RX_OVRN 0x10 |
| #define LAN91_INT_ALLOC 0x08 |
| #define LAN91_INT_TX_EMPTY 0x04 |
| #define LAN91_INT_TX 0x02 |
| #define LAN91_MT (LAN91_BASE_ADDR + 0x00) |
| #define LAN91_MGMT (LAN91_BASE_ADDR + 0x08) |
| #define LAN91_MGMT_MDOE 0x08 |
LAN91_MGMT bit mask, enables MDO pin.
| #define LAN91_MGMT_MCLK 0x04 |
LAN91_MGMT bit mask, drives MDCLK pin.
| #define LAN91_MGMT_MDI 0x02 |
LAN91_MGMT bit mask, reflects MDI pin status.
| #define LAN91_MGMT_MDO 0x01 |
LAN91_MGMT bit mask, drives MDO pin.
| #define LAN91_REV (LAN91_BASE_ADDR + 0x0A) |
| #define LAN91_ERCV (LAN91_BASE_ADDR + 0x0C) |
| #define LAN91_PHYCR_RST 0x8000 |
LAN91_PHYCR bit mask, resets PHY.
| #define LAN91_PHYCR_LPBK 0x4000 |
LAN91_PHYCR bit mask, .
| #define LAN91_PHYCR_SPEED 0x2000 |
LAN91_PHYCR bit mask, .
| #define LAN91_PHYCR_ANEG_EN 0x1000 |
LAN91_PHYCR bit mask, .
| #define LAN91_PHYCR_PDN 0x0800 |
LAN91_PHYCR bit mask, .
| #define LAN91_PHYCR_MII_DIS 0x0400 |
LAN91_PHYCR bit mask, .
| #define LAN91_PHYCR_ANEG_RST 0x0200 |
LAN91_PHYCR bit mask, .
| #define LAN91_PHYCR_DPLX 0x0100 |
LAN91_PHYCR bit mask, .
| #define LAN91_PHYCR_COLST 0x0080 |
LAN91_PHYCR bit mask, .
| #define LAN91_PHYSR_CAP_T4 0x8000 |
LAN91_PHYSR bit mask, indicates 100BASE-T4 capability.
| #define LAN91_PHYSR_CAP_TXF 0x4000 |
LAN91_PHYSR bit mask, indicates 100BASE-TX full duplex capability.
| #define LAN91_PHYSR_CAP_TXH 0x2000 |
LAN91_PHYSR bit mask, indicates 100BASE-TX half duplex capability.
| #define LAN91_PHYSR_CAP_TF 0x1000 |
LAN91_PHYSR bit mask, indicates 10BASE-T full duplex capability.
| #define LAN91_PHYSR_CAP_TH 0x0800 |
LAN91_PHYSR bit mask, indicates 10BASE-T half duplex capability.
| #define LAN91_PHYSR_CAP_SUPR 0x0040 |
LAN91_PHYSR bit mask, indicates preamble suppression capability.
| #define LAN91_PHYSR_ANEG_ACK 0x0020 |
LAN91_PHYSR bit mask, auto-negotiation completed.
| #define LAN91_PHYSR_REM_FLT 0x0010 |
LAN91_PHYSR bit mask, remote fault detected.
| #define LAN91_PHYSR_CAP_ANEG 0x0008 |
LAN91_PHYSR bit mask, indicates auto-negotiation capability.
| #define LAN91_PHYSR_LINK 0x0004 |
LAN91_PHYSR bit mask, valid link status.
| #define LAN91_PHYSR_JAB 0x0002 |
LAN91_PHYSR bit mask, jabber collision detected.
| #define LAN91_PHYSR_EXREG 0x0001 |
LAN91_PHYSR bit mask, extended capabilities available.
| #define LAN91_PHYANAD 4 |
| #define LAN91_PHYANAD_NP 0x8000 |
LAN91_PHYANAD bit mask, exchanging next page information.
| #define LAN91_PHYANAD_ACK 0x4000 |
LAN91_PHYANAD bit mask, acknowledged.
| #define LAN91_PHYANAD_RF 0x2000 |
LAN91_PHYANAD bit mask, remote fault.
| #define LAN91_PHYANAD_T4 0x0200 |
LAN91_PHYANAD bit mask, indicates 100BASE-T4 capability.
| #define LAN91_PHYANAD_TX_FDX 0x0100 |
LAN91_PHYANAD bit mask, indicates 100BASE-TX full duplex capability.
| #define LAN91_PHYANAD_TX_HDX 0x0080 |
LAN91_PHYANAD bit mask, indicates 100BASE-TX half duplex capability.
| #define LAN91_PHYANAD_10FDX 0x0040 |
LAN91_PHYANAD bit mask, indicates 10BASE-T full duplex capability.
| #define LAN91_PHYANAD_10_HDX 0x0020 |
LAN91_PHYANAD bit mask, indicates 10BASE-T half duplex capability.
| #define LAN91_PHYANAD_CSMA 0x0001 |
LAN91_PHYANAD bit mask, indicates 802.3 CSMA capability.
| #define LAN91_PHYANRC 5 |
| #define LAN91_PHYSOR_INT 0x8000 |
LAN91_PHYSOR bit mask, interrupt bits changed.
| #define LAN91_PHYSOR_LNKFAIL 0x4000 |
LAN91_PHYSOR bit mask, link failure detected.
| #define LAN91_PHYSOR_LOSSSYNC 0x2000 |
LAN91_PHYSOR bit mask, descrambler sync lost detected.
| #define LAN91_PHYSOR_CWRD 0x1000 |
LAN91_PHYSOR bit mask, code word error detected.
| #define LAN91_PHYSOR_SSD 0x0800 |
LAN91_PHYSOR bit mask, start of stream error detected.
| #define LAN91_PHYSOR_ESD 0x0400 |
LAN91_PHYSOR bit mask, end of stream error detected.
| #define LAN91_PHYSOR_RPOL 0x0200 |
LAN91_PHYSOR bit mask, reverse polarity detected.
| #define LAN91_PHYSOR_JAB 0x0100 |
LAN91_PHYSOR bit mask, jabber detected.
| #define LAN91_PHYSOR_SPDDET 0x0080 |
LAN91_PHYSOR bit mask, 100/10 speed detected.
| #define LAN91_PHYSOR_DPLXDET 0x0040 |
LAN91_PHYSOR bit mask, duplex detected.
| #define LAN91_PHYMSK_MINT 0x8000 |
LAN91_PHYMSK bit mask, enables LAN91_PHYSOR_INT interrupt.
| #define LAN91_PHYMSK_MLNKFAIL 0x4000 |
LAN91_PHYMSK bit mask, enables LAN91_PHYSOR_LNKFAIL interrupt.
| #define LAN91_PHYMSK_MLOSSSYN 0x2000 |
LAN91_PHYMSK bit mask, enables LAN91_PHYSOR_LOSSSYNC interrupt.
| #define LAN91_PHYMSK_MCWRD 0x1000 |
LAN91_PHYMSK bit mask, enables LAN91_PHYSOR_CWRD interrupt.
| #define LAN91_PHYMSK_MSSD 0x0800 |
LAN91_PHYMSK bit mask, enables LAN91_PHYSOR_SSD interrupt.
| #define LAN91_PHYMSK_MESD 0x0400 |
LAN91_PHYMSK bit mask, enables LAN91_PHYSOR_ESD interrupt.
| #define LAN91_PHYMSK_MRPOL 0x0200 |
LAN91_PHYMSK bit mask, enables LAN91_PHYSOR_RPOL interrupt.
| #define LAN91_PHYMSK_MJAB 0x0100 |
LAN91_PHYMSK bit mask, enables LAN91_PHYSOR_JAB interrupt.
| #define LAN91_PHYMSK_MSPDDT 0x0080 |
LAN91_PHYMSK bit mask, enables LAN91_PHYSOR_SPDDET interrupt.
| #define LAN91_PHYMSK_MDPLDT 0x0040 |
LAN91_PHYMSK bit mask, enables LAN91_PHYSOR_DPLXDET interrupt.
| #define nic_outlb | ( | addr, | |
| val | |||
| ) | (*(volatile uint8_t *)(addr) = (val)) |
Definition at line 110 of file lan91.c.
Referenced by NicRxLanc().
| #define nic_outhb | ( | addr, | |
| val | |||
| ) | (*(volatile uint8_t *)((addr) + 1) = (val)) |
| #define nic_outwx | ( | addr, | |
| val | |||
| ) | (*(volatile uint16_t *)(addr) = (val)) |
| #define nic_outw | ( | addr, | |
| val | |||
| ) |
| #define nic_inlb | ( | addr | ) | (*(volatile uint8_t *)(addr)) |
Definition at line 118 of file lan91.c.
Referenced by NicRxLanc().
| #define nic_inhb | ( | addr | ) | (*(volatile uint8_t *)((addr) + 1)) |
| void NicRxLanc | ( | void * | arg | ) |
Definition at line 749 of file lan91.c.
References _NUTDEVICE::dev_dcb, _NUTDEVICE::dev_icb, ETHER_IS_UNICAST, ifnet::if_mac, ifnet::if_recv, LAN91_MSK, LAN91_RX_POLLTIME, LAN91_SIGNAL, NICINFO::ni_rx_packets, NICINFO::ni_rx_rdy, nic_inlb, nic_outlb, NUT_IRQMODE_RISINGEDGE, NutEventPost(), NutEventWait(), NutIrqEnable(), NutIrqSetMode(), NutSleep(), and NutThreadSetPriority().
{
0,
{'e', 't', 'h', '0', 0, 0, 0, 0, 0},
IFTYP_NET,
0,
0,
&ifn_eth0,
&dcb_eth0,
Lan91Init,
Lan91IOCtl,
0,
0,
0,
0,
0,
0
}
Device information structure.
A pointer to this structure must be passed to NutRegisterDevice() to bind this Ethernet device driver to the Nut/OS kernel. An application may then call NutNetIfConfig() with the name eth0 of this driver to initialize the network interface.