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Nut/OS
4.10.3
API Reference
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Nut/OS
4.10.3
API Reference
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Serial peripheral interface registers. More...
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SPI Control Register | |
| #define | SPI_CR_OFF 0x00000000 |
| Control register offset. | |
| #define | SPI_SPIEN 0x00000001 |
| SPI enable. | |
| #define | SPI_SPIDIS 0x00000002 |
| SPI disable. | |
| #define | SPI_SWRST 0x00000080 |
| Software reset. | |
| #define | SPI_LASTXFER 0x01000000 |
| Last transfer. | |
SPI Mode Register | |
| #define | SPI_MR_OFF 0x00000004 |
| Mode register offset. | |
| #define | SPI_MSTR 0x00000001 |
| Master mode. | |
| #define | SPI_PS 0x00000002 |
| Peripheral select. | |
| #define | SPI_PCSDEC 0x00000004 |
| Chip select decode. | |
| #define | SPI_FDIV 0x00000008 |
| Clock selection. | |
| #define | SPI_MODFDIS 0x00000010 |
| Mode fault detection. | |
| #define | SPI_LLB 0x00000080 |
| Local loopback enable. | |
| #define | SPI_PCS 0x000F0000 |
| Peripheral chip select mask. | |
| #define | SPI_PCS_0 0x000E0000 |
| Peripheral chip select 0. | |
| #define | SPI_PCS_1 0x000D0000 |
| Peripheral chip select 1. | |
| #define | SPI_PCS_2 0x000B0000 |
| Peripheral chip select 2. | |
| #define | SPI_PCS_3 0x00070000 |
| Peripheral chip select 3. | |
| #define | SPI_PCS_LSB 16 |
| Least significant bit of peripheral chip select. | |
| #define | SPI_DLYBCS 0xFF000000 |
| Mask for delay between chip selects. | |
| #define | SPI_DLYBCS_LSB 24 |
| Least significant bit of delay between chip selects. | |
SPI Receive Data Register | |
| #define | SPI_RDR_OFF 0x00000008 |
| Receive data register offset. | |
| #define | SPI_RD 0x0000FFFF |
| Receive data mask. | |
| #define | SPI_RD_LSB 0 |
| Least significant bit of receive data. | |
SPI Transmit Data Register | |
| #define | SPI_TDR_OFF 0x0000000C |
| Transmit data register offset. | |
| #define | SPI_TD 0x0000FFFF |
| Transmit data mask. | |
| #define | SPI_TD_LSB 0 |
| Least significant bit of transmit data. | |
SPI Status and Interrupt Register | |
| #define | SPI_SR_OFF 0x00000010 |
| Status register offset. | |
| #define | SPI_IER_OFF 0x00000014 |
| Interrupt enable register offset. | |
| #define | SPI_IDR_OFF 0x00000018 |
| Interrupt disable register offset. | |
| #define | SPI_IMR_OFF 0x0000001C |
| Interrupt mask register offset. | |
| #define | SPI_RDRF 0x00000001 |
| Receive data register full. | |
| #define | SPI_TDRE 0x00000002 |
| Transmit data register empty. | |
| #define | SPI_MODF 0x00000004 |
| Mode fault error. | |
| #define | SPI_OVRES 0x00000008 |
| Overrun error status. | |
| #define | SPI_ENDRX 0x00000010 |
| End of RX buffer. | |
| #define | SPI_ENDTX 0x00000020 |
| End of TX buffer. | |
| #define | SPI_RXBUFF 0x00000040 |
| RX buffer full. | |
| #define | SPI_TXBUFE 0x00000080 |
| TX buffer empty. | |
| #define | SPI_NSSR 0x00000100 |
| NSS rising. | |
| #define | SPI_TXEMPTY 0x00000200 |
| Transmission register empty. | |
| #define | SPI_SPIENS 0x00010000 |
| SPI enable status. | |
SPI Chip Select Registers | |
| #define | SPI_CSR0_OFF 0x00000030 |
| Chip select register 0 offset. | |
| #define | SPI_CSR1_OFF 0x00000034 |
| Chip select register 1 offset. | |
| #define | SPI_CSR2_OFF 0x00000038 |
| Chip select register 2 offset. | |
| #define | SPI_CSR3_OFF 0x0000003C |
| Chip select register 3 offset. | |
| #define | SPI_CPOL 0x00000001 |
| Clock polarity. | |
| #define | SPI_NCPHA 0x00000002 |
| Clock phase. | |
| #define | SPI_CSAAT 0x00000008 |
| Chip select active after transfer. | |
| #define | SPI_BITS 0x000000F0 |
| Bits per transfer mask. | |
| #define | SPI_BITS_8 0x00000000 |
| 8 bits per transfer. | |
| #define | SPI_BITS_9 0x00000010 |
| 9 bits per transfer. | |
| #define | SPI_BITS_10 0x00000020 |
| 10 bits per transfer. | |
| #define | SPI_BITS_11 0x00000030 |
| 11 bits per transfer. | |
| #define | SPI_BITS_12 0x00000040 |
| 12 bits per transfer. | |
| #define | SPI_BITS_13 0x00000050 |
| 13 bits per transfer. | |
| #define | SPI_BITS_14 0x00000060 |
| 14 bits per transfer. | |
| #define | SPI_BITS_15 0x00000070 |
| 15 bits per transfer. | |
| #define | SPI_BITS_16 0x00000080 |
| 16 bits per transfer. | |
| #define | SPI_BITS_LSB 4 |
| Least significant bit of bits per transfer. | |
| #define | SPI_SCBR 0x0000FF00 |
| Serial clock baud rate mask. | |
| #define | SPI_SCBR_LSB 8 |
| Least significant bit of serial clock baud rate. | |
| #define | SPI_DLYBS 0x00FF0000 |
| Delay before SPCK mask. | |
| #define | SPI_DLYBS_LSB 16 |
| Least significant bit of delay before SPCK. | |
| #define | SPI_DLYBCT 0xFF000000 |
| Delay between consecutive transfers mask. | |
| #define | SPI_DLYBCT_LSB 24 |
| Least significant bit of delay between consecutive transfers. | |
Serial peripheral interface registers.
| #define SPI_CR_OFF 0x00000000 |
Control register offset.
Definition at line 43 of file at91_spi.h.
Referenced by At91SpiDisable(), At91SpiEnable(), and At91SpiReset().
| #define SPI_SPIEN 0x00000001 |
SPI enable.
Definition at line 45 of file at91_spi.h.
Referenced by At91SpiBus0Select(), and At91SpiEnable().
| #define SPI_SPIDIS 0x00000002 |
| #define SPI_SWRST 0x00000080 |
| #define SPI_LASTXFER 0x01000000 |
Last transfer.
Definition at line 48 of file at91_spi.h.
| #define SPI_MR_OFF 0x00000004 |
Mode register offset.
Definition at line 53 of file at91_spi.h.
Referenced by At91SpiGetCsDelay(), At91SpiGetModeFlags(), At91SpiReset(), At91SpiSetCsDelay(), At91SpiSetModeFlags(), and At91SpiTransfer2().
| #define SPI_MSTR 0x00000001 |
Master mode.
Definition at line 55 of file at91_spi.h.
Referenced by At91SpiBusNodeInit(), At91SpiGetModeFlags(), At91SpiReset(), At91SpiSetModeFlags(), and FeederThread().
| #define SPI_PS 0x00000002 |
Peripheral select.
Definition at line 56 of file at91_spi.h.
| #define SPI_PCSDEC 0x00000004 |
Chip select decode.
Definition at line 57 of file at91_spi.h.
Referenced by At91SpiGetModeFlags(), and At91SpiSetModeFlags().
| #define SPI_FDIV 0x00000008 |
Clock selection.
Definition at line 58 of file at91_spi.h.
| #define SPI_MODFDIS 0x00000010 |
Mode fault detection.
Definition at line 59 of file at91_spi.h.
Referenced by At91SpiBusNodeInit(), At91SpiGetModeFlags(), At91SpiReset(), At91SpiSetModeFlags(), At91SpiSetup(), and FeederThread().
| #define SPI_LLB 0x00000080 |
Local loopback enable.
Definition at line 60 of file at91_spi.h.
Referenced by At91SpiGetModeFlags(), At91SpiSetModeFlags(), and At91SpiSetup().
| #define SPI_PCS 0x000F0000 |
Peripheral chip select mask.
Definition at line 61 of file at91_spi.h.
Referenced by At91SpiReset(), and At91SpiTransfer2().
| #define SPI_PCS_0 0x000E0000 |
Peripheral chip select 0.
Definition at line 62 of file at91_spi.h.
Referenced by At91SpiBusNodeInit(), and At91SpiTransfer2().
| #define SPI_PCS_1 0x000D0000 |
Peripheral chip select 1.
Definition at line 63 of file at91_spi.h.
Referenced by At91SpiBusNodeInit(), and At91SpiTransfer2().
| #define SPI_PCS_2 0x000B0000 |
Peripheral chip select 2.
Definition at line 64 of file at91_spi.h.
Referenced by At91SpiBusNodeInit(), and At91SpiTransfer2().
| #define SPI_PCS_3 0x00070000 |
Peripheral chip select 3.
Definition at line 65 of file at91_spi.h.
Referenced by At91SpiBusNodeInit(), and At91SpiTransfer2().
| #define SPI_PCS_LSB 16 |
Least significant bit of peripheral chip select.
Definition at line 66 of file at91_spi.h.
| #define SPI_DLYBCS 0xFF000000 |
Mask for delay between chip selects.
Definition at line 67 of file at91_spi.h.
Referenced by At91SpiSetCsDelay().
| #define SPI_DLYBCS_LSB 24 |
Least significant bit of delay between chip selects.
Definition at line 68 of file at91_spi.h.
Referenced by At91SpiGetCsDelay(), At91SpiReset(), and At91SpiSetCsDelay().
| #define SPI_RDR_OFF 0x00000008 |
Receive data register offset.
Definition at line 73 of file at91_spi.h.
| #define SPI_RD 0x0000FFFF |
Receive data mask.
Definition at line 75 of file at91_spi.h.
| #define SPI_RD_LSB 0 |
Least significant bit of receive data.
Definition at line 76 of file at91_spi.h.
| #define SPI_TDR_OFF 0x0000000C |
Transmit data register offset.
Definition at line 81 of file at91_spi.h.
Referenced by At91SpiBus0Transfer().
| #define SPI_TD 0x0000FFFF |
Transmit data mask.
Definition at line 83 of file at91_spi.h.
| #define SPI_TD_LSB 0 |
Least significant bit of transmit data.
Definition at line 84 of file at91_spi.h.
| #define SPI_SR_OFF 0x00000010 |
| #define SPI_IER_OFF 0x00000014 |
Interrupt enable register offset.
Definition at line 90 of file at91_spi.h.
Referenced by At91SpiBus0Transfer(), and At91SpiTransfer2().
| #define SPI_IDR_OFF 0x00000018 |
Interrupt disable register offset.
Definition at line 91 of file at91_spi.h.
Referenced by At91SpiBus0Transfer(), At91SpiBusNodeInit(), and At91SpiTransfer2().
| #define SPI_IMR_OFF 0x0000001C |
Interrupt mask register offset.
Definition at line 92 of file at91_spi.h.
| #define SPI_RDRF 0x00000001 |
Receive data register full.
Definition at line 94 of file at91_spi.h.
Referenced by At91SpiBus0Transfer().
| #define SPI_TDRE 0x00000002 |
Transmit data register empty.
Definition at line 95 of file at91_spi.h.
| #define SPI_MODF 0x00000004 |
Mode fault error.
Definition at line 96 of file at91_spi.h.
| #define SPI_OVRES 0x00000008 |
Overrun error status.
Definition at line 97 of file at91_spi.h.
| #define SPI_ENDRX 0x00000010 |
End of RX buffer.
Definition at line 98 of file at91_spi.h.
| #define SPI_ENDTX 0x00000020 |
End of TX buffer.
Definition at line 99 of file at91_spi.h.
| #define SPI_RXBUFF 0x00000040 |
| #define SPI_TXBUFE 0x00000080 |
TX buffer empty.
Definition at line 101 of file at91_spi.h.
| #define SPI_NSSR 0x00000100 |
NSS rising.
Definition at line 102 of file at91_spi.h.
| #define SPI_TXEMPTY 0x00000200 |
Transmission register empty.
Definition at line 103 of file at91_spi.h.
| #define SPI_SPIENS 0x00010000 |
SPI enable status.
Definition at line 104 of file at91_spi.h.
| #define SPI_CSR0_OFF 0x00000030 |
Chip select register 0 offset.
Definition at line 109 of file at91_spi.h.
Referenced by At91SpiGetBits(), At91SpiGetModeFlags(), At91SpiGetSckDelay(), At91SpiGetTxDelay(), At91SpiSetBits(), At91SpiSetModeFlags(), At91SpiSetRate(), At91SpiSetSckDelay(), and At91SpiSetTxDelay().
| #define SPI_CSR1_OFF 0x00000034 |
Chip select register 1 offset.
Definition at line 110 of file at91_spi.h.
Referenced by At91SpiSetRate().
| #define SPI_CSR2_OFF 0x00000038 |
Chip select register 2 offset.
Definition at line 111 of file at91_spi.h.
Referenced by At91SpiSetRate().
| #define SPI_CSR3_OFF 0x0000003C |
Chip select register 3 offset.
Definition at line 112 of file at91_spi.h.
Referenced by At91SpiSetRate().
| #define SPI_CPOL 0x00000001 |
Clock polarity.
Definition at line 114 of file at91_spi.h.
Referenced by At91SpiGetModeFlags(), At91SpiSetModeFlags(), and At91SpiSetup().
| #define SPI_NCPHA 0x00000002 |
Clock phase.
Definition at line 115 of file at91_spi.h.
Referenced by At91SpiGetModeFlags(), At91SpiSetModeFlags(), At91SpiSetup(), and FeederThread().
| #define SPI_CSAAT 0x00000008 |
Chip select active after transfer.
Definition at line 116 of file at91_spi.h.
Referenced by At91SpiSetModeFlags(), and At91SpiSetup().
| #define SPI_BITS 0x000000F0 |
Bits per transfer mask.
Definition at line 117 of file at91_spi.h.
Referenced by At91SpiGetBits(), At91SpiSetBits(), and At91SpiSetup().
| #define SPI_BITS_8 0x00000000 |
| #define SPI_BITS_9 0x00000010 |
9 bits per transfer.
Definition at line 119 of file at91_spi.h.
Referenced by At91SpiGetBits(), and At91SpiSetBits().
| #define SPI_BITS_10 0x00000020 |
10 bits per transfer.
Definition at line 120 of file at91_spi.h.
Referenced by At91SpiGetBits(), and At91SpiSetBits().
| #define SPI_BITS_11 0x00000030 |
11 bits per transfer.
Definition at line 121 of file at91_spi.h.
Referenced by At91SpiGetBits(), and At91SpiSetBits().
| #define SPI_BITS_12 0x00000040 |
12 bits per transfer.
Definition at line 122 of file at91_spi.h.
Referenced by At91SpiGetBits(), and At91SpiSetBits().
| #define SPI_BITS_13 0x00000050 |
13 bits per transfer.
Definition at line 123 of file at91_spi.h.
Referenced by At91SpiGetBits(), and At91SpiSetBits().
| #define SPI_BITS_14 0x00000060 |
14 bits per transfer.
Definition at line 124 of file at91_spi.h.
Referenced by At91SpiGetBits(), and At91SpiSetBits().
| #define SPI_BITS_15 0x00000070 |
15 bits per transfer.
Definition at line 125 of file at91_spi.h.
Referenced by At91SpiGetBits(), and At91SpiSetBits().
| #define SPI_BITS_16 0x00000080 |
16 bits per transfer.
Definition at line 126 of file at91_spi.h.
Referenced by At91SpiGetBits(), and At91SpiSetBits().
| #define SPI_BITS_LSB 4 |
Least significant bit of bits per transfer.
Definition at line 127 of file at91_spi.h.
Referenced by At91SpiSetup().
| #define SPI_SCBR 0x0000FF00 |
Serial clock baud rate mask.
Definition at line 128 of file at91_spi.h.
Referenced by At91SpiSetRate(), and At91SpiSetup().
| #define SPI_SCBR_LSB 8 |
Least significant bit of serial clock baud rate.
Definition at line 129 of file at91_spi.h.
Referenced by At91SpiSetRate(), At91SpiSetup(), and FeederThread().
| #define SPI_DLYBS 0x00FF0000 |
Delay before SPCK mask.
Definition at line 130 of file at91_spi.h.
Referenced by At91SpiSetSckDelay().
| #define SPI_DLYBS_LSB 16 |
Least significant bit of delay before SPCK.
Definition at line 131 of file at91_spi.h.
Referenced by At91SpiGetSckDelay(), and At91SpiSetSckDelay().
| #define SPI_DLYBCT 0xFF000000 |
Delay between consecutive transfers mask.
Definition at line 132 of file at91_spi.h.
Referenced by At91SpiSetTxDelay().
| #define SPI_DLYBCT_LSB 24 |
Least significant bit of delay between consecutive transfers.
Definition at line 133 of file at91_spi.h.
Referenced by At91SpiGetTxDelay(), and At91SpiSetTxDelay().