Watchdog Registers

Watchdog timer registers. More...

Collaboration diagram for Watchdog Registers:

Watch Dog Overflow Mode Register
#define	WD_OMR   (WD_BASE + 0x00)
	Overflow mode register address.
#define	WD_WDEN   0x00000001
	Watch Dog enable.
#define	WD_RSTEN   0x00000002
	Internal reset enable.
#define	WD_IRQEN   0x00000004
	Interrupt enable.
#define	WD_EXTEN   0x00000008
	External signal enable.
#define	WD_OKEY   0x00002340
	Overflow mode register access key.
Watch Dog Clock Register
#define	WD_CMR   (WD_BASE + 0x04)
	Clock mode register address.
#define	WD_WDCLKS   0x00000003
	Clock selection mask.
#define	WD_WDCLKS_MCK8   0x00000000
	Selects MCK/8.
#define	WD_WDCLKS_MCK32   0x00000001
	Selects MCK/32.
#define	WD_WDCLKS_MCK128   0x00000002
	Selects MCK/128.
#define	WD_WDCLKS_MCK1024   0x00000003
	Selects MCK/1024.
#define	WD_HPCV   0x0000003C
	High preload counter value.
#define	WD_CKEY   (0x06E<<7)
	Clock register access key.
Watch Dog Control Register
#define	WD_CR   (WD_BASE + 0x08)
	Control register address.
#define	WD_RSTKEY   0x0000C071
	Watch Dog restart key.
Watch Dog Status Register
#define	WD_SR   (WD_BASE + 0x0C)
	Status register address.
#define	WD_WDOVF   0x00000001
	Watch Dog overflow status.

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Detailed Description

Watchdog timer registers.

The Watch Dog is used to prevent system lock-up if the software becomes trapped in a deadlock. It can generate an internal reset or interrupt.

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Define Documentation

#define WD_OMR   (WD_BASE + 0x00)

Overflow mode register address.

Definition at line 57 of file at91_wd.h.

Referenced by At91WatchDogDisable(), At91WatchDogEnable(), and At91WatchDogStart().

#define WD_WDEN   0x00000001

Watch Dog enable.

Definition at line 58 of file at91_wd.h.

Referenced by At91WatchDogDisable(), At91WatchDogEnable(), and At91WatchDogStart().

#define WD_RSTEN   0x00000002

Internal reset enable.

Definition at line 59 of file at91_wd.h.

Referenced by At91WatchDogStart().

#define WD_IRQEN   0x00000004

Interrupt enable.

Definition at line 60 of file at91_wd.h.

#define WD_EXTEN   0x00000008

External signal enable.

Definition at line 61 of file at91_wd.h.

#define WD_OKEY   0x00002340

Overflow mode register access key.

Definition at line 62 of file at91_wd.h.

Referenced by At91WatchDogDisable(), At91WatchDogEnable(), and At91WatchDogStart().

#define WD_CMR   (WD_BASE + 0x04)

Clock mode register address.

Definition at line 67 of file at91_wd.h.

Referenced by At91WatchDogStart().

#define WD_WDCLKS   0x00000003

Clock selection mask.

Definition at line 68 of file at91_wd.h.

#define WD_WDCLKS_MCK8   0x00000000

Selects MCK/8.

Definition at line 69 of file at91_wd.h.

Referenced by At91WatchDogStart().

#define WD_WDCLKS_MCK32   0x00000001

Selects MCK/32.

Definition at line 70 of file at91_wd.h.

Referenced by At91WatchDogStart().

#define WD_WDCLKS_MCK128   0x00000002

Selects MCK/128.

Definition at line 71 of file at91_wd.h.

Referenced by At91WatchDogStart().

#define WD_WDCLKS_MCK1024   0x00000003

Selects MCK/1024.

Definition at line 72 of file at91_wd.h.

Referenced by At91WatchDogStart().

#define WD_HPCV   0x0000003C

High preload counter value.

Definition at line 73 of file at91_wd.h.

Referenced by At91WatchDogStart().

#define WD_CKEY   (0x06E<<7)

Clock register access key.

Definition at line 74 of file at91_wd.h.

Referenced by At91WatchDogStart().

#define WD_CR   (WD_BASE + 0x08)

Control register address.

Definition at line 79 of file at91_wd.h.

Referenced by At91WatchDogRestart().

#define WD_RSTKEY   0x0000C071

Watch Dog restart key.

Definition at line 80 of file at91_wd.h.

Referenced by At91WatchDogRestart().

#define WD_SR   (WD_BASE + 0x0C)

Status register address.

Definition at line 85 of file at91_wd.h.

#define WD_WDOVF   0x00000001

Watch Dog overflow status.

Definition at line 86 of file at91_wd.h.