Nut/OS  5.0.5
API Reference
Data Structures | Modules | Defines | Functions
RCC
STM32F10x_StdPeriph_Driver | STM32F2xx_StdPeriph_Driver | STM32F4xx_StdPeriph_Driver | STM32L1xx_StdPeriph_Driver

RCC driver modules. More...

Collaboration diagram for RCC:

Data Structures

struct  RCC_ClocksTypeDef

Modules

 RCC_Exported_Types
 RCC_Exported_Constants
 RCC_Exported_Macros
 RCC_Exported_Functions
 RCC_Private_TypesDefinitions
 RCC_Private_Defines
 RCC_Private_Macros
 RCC_Private_Variables
 RCC_Private_FunctionPrototypes
 RCC_Private_Functions

Defines

#define RCC_OFFSET   (RCC_BASE - PERIPH_BASE)
#define CR_OFFSET   (RCC_OFFSET + 0x00)
#define HSION_BitNumber   0x00
#define CR_HSION_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
#define CSSON_BitNumber   0x13
#define CR_CSSON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
#define PLLON_BitNumber   0x18
#define CR_PLLON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
#define PLLI2SON_BitNumber   0x1A
#define CR_PLLI2SON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
#define CFGR_OFFSET   (RCC_OFFSET + 0x08)
#define I2SSRC_BitNumber   0x17
#define CFGR_I2SSRC_BB   (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
#define BDCR_OFFSET   (RCC_OFFSET + 0x70)
#define RTCEN_BitNumber   0x0F
#define BDCR_RTCEN_BB   (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
#define BDRST_BitNumber   0x10
#define BDCR_BDRST_BB   (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
#define CSR_OFFSET   (RCC_OFFSET + 0x74)
#define LSION_BitNumber   0x00
#define CSR_LSION_BB   (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
#define CFGR_MCO2_RESET_MASK   ((uint32_t)0x07FFFFFF)
#define CFGR_MCO1_RESET_MASK   ((uint32_t)0xF89FFFFF)
#define FLAG_MASK   ((uint8_t)0x1F)
#define CR_BYTE3_ADDRESS   ((uint32_t)0x40023802)
#define CIR_BYTE2_ADDRESS   ((uint32_t)(RCC_BASE + 0x0C + 0x01))
#define CIR_BYTE3_ADDRESS   ((uint32_t)(RCC_BASE + 0x0C + 0x02))
#define BDCR_ADDRESS   (PERIPH_BASE + BDCR_OFFSET)
#define RCC_OFFSET   (RCC_BASE - PERIPH_BASE)
#define CR_OFFSET   (RCC_OFFSET + 0x00)
#define HSION_BitNumber   0x00
#define CR_HSION_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
#define CSSON_BitNumber   0x13
#define CR_CSSON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
#define PLLON_BitNumber   0x18
#define CR_PLLON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
#define PLLI2SON_BitNumber   0x1A
#define CR_PLLI2SON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
#define CFGR_OFFSET   (RCC_OFFSET + 0x08)
#define I2SSRC_BitNumber   0x17
#define CFGR_I2SSRC_BB   (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
#define BDCR_OFFSET   (RCC_OFFSET + 0x70)
#define RTCEN_BitNumber   0x0F
#define BDCR_RTCEN_BB   (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
#define BDRST_BitNumber   0x10
#define BDCR_BDRST_BB   (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
#define CSR_OFFSET   (RCC_OFFSET + 0x74)
#define LSION_BitNumber   0x00
#define CSR_LSION_BB   (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
#define CFGR_MCO2_RESET_MASK   ((uint32_t)0x07FFFFFF)
#define CFGR_MCO1_RESET_MASK   ((uint32_t)0xF89FFFFF)
#define FLAG_MASK   ((uint8_t)0x1F)
#define CR_BYTE3_ADDRESS   ((uint32_t)0x40023802)
#define CIR_BYTE2_ADDRESS   ((uint32_t)(RCC_BASE + 0x0C + 0x01))
#define CIR_BYTE3_ADDRESS   ((uint32_t)(RCC_BASE + 0x0C + 0x02))
#define BDCR_ADDRESS   (PERIPH_BASE + BDCR_OFFSET)
#define RCC_OFFSET   (RCC_BASE - PERIPH_BASE)
#define CR_OFFSET   (RCC_OFFSET + 0x00)
#define HSION_BitNumber   0x00
#define CR_HSION_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
#define MSION_BitNumber   0x08
#define CR_MSION_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))
#define PLLON_BitNumber   0x18
#define CR_PLLON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
#define CSSON_BitNumber   0x1C
#define CR_CSSON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
#define CSR_OFFSET   (RCC_OFFSET + 0x34)
#define LSION_BitNumber   0x00
#define CSR_LSION_BB   (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
#define RTCEN_BitNumber   0x16
#define CSR_RTCEN_BB   (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))
#define RTCRST_BitNumber   0x17
#define CSR_RTCRST_BB   (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))
#define FLAG_MASK   ((uint8_t)0x1F)
#define CR_BYTE3_ADDRESS   ((uint32_t)0x40023802)
#define ICSCR_BYTE4_ADDRESS   ((uint32_t)0x40023807)
#define CFGR_BYTE3_ADDRESS   ((uint32_t)0x4002380A)
#define CFGR_BYTE4_ADDRESS   ((uint32_t)0x4002380B)
#define CIR_BYTE2_ADDRESS   ((uint32_t)0x4002380D)
#define CIR_BYTE3_ADDRESS   ((uint32_t)0x4002380E)
#define CSR_BYTE2_ADDRESS   ((uint32_t)0x40023835)

Functions

void RCC_DeInit (void)
 Resets the RCC clock configuration to the default reset state.
ErrorStatus RCC_WaitForHSEStartUp (void)
 Waits for HSE start-up.
void RCC_AdjustHSICalibrationValue (uint8_t HSICalibrationValue)
 Adjusts the Internal High Speed oscillator (HSI) calibration value.
void RCC_HSICmd (FunctionalState NewState)
 Enables or disables the Internal High Speed oscillator (HSI).
void RCC_LSEConfig (uint8_t RCC_LSE)
 Configures the External Low Speed oscillator (LSE).
void RCC_LSICmd (FunctionalState NewState)
 Enables or disables the Internal Low Speed oscillator (LSI).
void RCC_PLLCmd (FunctionalState NewState)
 Enables or disables the PLL.
void RCC_ClockSecuritySystemCmd (FunctionalState NewState)
 Enables or disables the Clock Security System.
void RCC_SYSCLKConfig (uint32_t RCC_SYSCLKSource)
 Configures the system clock (SYSCLK).
uint8_t RCC_GetSYSCLKSource (void)
 Returns the clock source used as system clock.
void RCC_HCLKConfig (uint32_t RCC_SYSCLK)
 Configures the AHB clock (HCLK).
void RCC_PCLK1Config (uint32_t RCC_HCLK)
 Configures the Low Speed APB clock (PCLK1).
void RCC_PCLK2Config (uint32_t RCC_HCLK)
 Configures the High Speed APB clock (PCLK2).
void RCC_GetClocksFreq (RCC_ClocksTypeDef *RCC_Clocks)
 Returns the frequencies of different on chip clocks.
void RCC_RTCCLKConfig (uint32_t RCC_RTCCLKSource)
 Configures the RTC clock (RTCCLK).
void RCC_RTCCLKCmd (FunctionalState NewState)
 Enables or disables the RTC clock.
void RCC_BackupResetCmd (FunctionalState NewState)
 Forces or releases the Backup domain reset.
void RCC_APB1PeriphClockCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Enables or disables the Low Speed APB (APB1) peripheral clock.
void RCC_APB2PeriphClockCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Enables or disables the High Speed APB (APB2) peripheral clock.
void RCC_APB1PeriphResetCmd (uint32_t RCC_APB1Periph, FunctionalState NewState)
 Forces or releases Low Speed APB (APB1) peripheral reset.
void RCC_APB2PeriphResetCmd (uint32_t RCC_APB2Periph, FunctionalState NewState)
 Forces or releases High Speed APB (APB2) peripheral reset.
void RCC_ITConfig (uint8_t RCC_IT, FunctionalState NewState)
 Enables or disables the specified RCC interrupts.
FlagStatus RCC_GetFlagStatus (uint8_t RCC_FLAG)
 Checks whether the specified RCC flag is set or not.
void RCC_ClearFlag (void)
 Clears the RCC reset flags.
ITStatus RCC_GetITStatus (uint8_t RCC_IT)
 Checks whether the specified RCC interrupt has occurred or not.
void RCC_ClearITPendingBit (uint8_t RCC_IT)
 Clears the RCC’s interrupt pending bits.
void RCC_MSIRangeConfig (uint32_t RCC_MSIRange)
 Configures the Internal Multi Speed oscillator (MSI) clock range.
void RCC_AdjustMSICalibrationValue (uint8_t MSICalibrationValue)
 Adjusts the Internal Multi Speed oscillator (MSI) calibration value.
void RCC_MSICmd (FunctionalState NewState)
 Enables or disables the Internal Multi Speed oscillator (MSI).
void RCC_PLLConfig (uint8_t RCC_PLLSource, uint8_t RCC_PLLMul, uint8_t RCC_PLLDiv)
 Configures the PLL clock source and multiplication factor.
void RCC_LSEClockSecuritySystemCmd (FunctionalState NewState)
void RCC_MCOConfig (uint8_t RCC_MCOSource, uint8_t RCC_MCODiv)
 Selects the clock source to output on MCO pin (PA8).
void RCC_RTCResetCmd (FunctionalState NewState)
 Forces or releases the RTC peripheral and associated resources reset.
void RCC_AHBPeriphClockCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
 Enables or disables the AHB peripheral clock.
void RCC_AHBPeriphResetCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
 Forces or releases AHB peripheral reset.
void RCC_AHBPeriphClockLPModeCmd (uint32_t RCC_AHBPeriph, FunctionalState NewState)
 Enables or disables the AHB peripheral clock during SLEEP mode.

Detailed Description

RCC driver modules.

Define Documentation

#define RCC_OFFSET   (RCC_BASE - PERIPH_BASE)
#define CR_OFFSET   (RCC_OFFSET + 0x00)
#define HSION_BitNumber   0x00
#define CR_HSION_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))

Referenced by RCC_HSICmd().

#define CSSON_BitNumber   0x13
#define CR_CSSON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))

Referenced by RCC_ClockSecuritySystemCmd().

#define PLLON_BitNumber   0x18
#define CR_PLLON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))

Referenced by RCC_PLLCmd().

#define PLLI2SON_BitNumber   0x1A
#define CR_PLLI2SON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))

Referenced by RCC_PLLI2SCmd().

#define CFGR_OFFSET   (RCC_OFFSET + 0x08)
#define I2SSRC_BitNumber   0x17
#define CFGR_I2SSRC_BB   (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))

Referenced by RCC_I2SCLKConfig().

#define BDCR_OFFSET   (RCC_OFFSET + 0x70)
#define RTCEN_BitNumber   0x0F
#define BDCR_RTCEN_BB   (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))

Referenced by RCC_RTCCLKCmd().

#define BDRST_BitNumber   0x10
#define BDCR_BDRST_BB   (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))

Referenced by RCC_BackupResetCmd().

#define CSR_OFFSET   (RCC_OFFSET + 0x74)
#define LSION_BitNumber   0x00
#define CSR_LSION_BB   (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))

Referenced by RCC_LSICmd().

#define CFGR_MCO2_RESET_MASK   ((uint32_t)0x07FFFFFF)

Referenced by RCC_MCO2Config().

#define CFGR_MCO1_RESET_MASK   ((uint32_t)0xF89FFFFF)

Referenced by RCC_MCO1Config().

#define FLAG_MASK   ((uint8_t)0x1F)

Referenced by RCC_GetFlagStatus().

#define CR_BYTE3_ADDRESS   ((uint32_t)0x40023802)

Referenced by RCC_HSEConfig().

#define CIR_BYTE2_ADDRESS   ((uint32_t)(RCC_BASE + 0x0C + 0x01))

Referenced by RCC_ITConfig().

#define CIR_BYTE3_ADDRESS   ((uint32_t)(RCC_BASE + 0x0C + 0x02))

Referenced by RCC_ClearITPendingBit().

#define BDCR_ADDRESS   (PERIPH_BASE + BDCR_OFFSET)

Referenced by RCC_LSEConfig().

#define RCC_OFFSET   (RCC_BASE - PERIPH_BASE)
#define CR_OFFSET   (RCC_OFFSET + 0x00)
#define HSION_BitNumber   0x00
#define CR_HSION_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
#define CSSON_BitNumber   0x13
#define CR_CSSON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
#define PLLON_BitNumber   0x18
#define CR_PLLON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
#define PLLI2SON_BitNumber   0x1A
#define CR_PLLI2SON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))

Referenced by RCC_PLLI2SCmd().

#define CFGR_OFFSET   (RCC_OFFSET + 0x08)
#define I2SSRC_BitNumber   0x17
#define CFGR_I2SSRC_BB   (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))

Referenced by RCC_I2SCLKConfig().

#define BDCR_OFFSET   (RCC_OFFSET + 0x70)
#define RTCEN_BitNumber   0x0F
#define BDCR_RTCEN_BB   (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
#define BDRST_BitNumber   0x10
#define BDCR_BDRST_BB   (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
#define CSR_OFFSET   (RCC_OFFSET + 0x74)
#define LSION_BitNumber   0x00
#define CSR_LSION_BB   (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
#define CFGR_MCO2_RESET_MASK   ((uint32_t)0x07FFFFFF)

Referenced by RCC_MCO2Config().

#define CFGR_MCO1_RESET_MASK   ((uint32_t)0xF89FFFFF)

Referenced by RCC_MCO1Config().

#define FLAG_MASK   ((uint8_t)0x1F)
#define CR_BYTE3_ADDRESS   ((uint32_t)0x40023802)

Referenced by RCC_HSEConfig().

#define CIR_BYTE2_ADDRESS   ((uint32_t)(RCC_BASE + 0x0C + 0x01))
#define CIR_BYTE3_ADDRESS   ((uint32_t)(RCC_BASE + 0x0C + 0x02))
#define BDCR_ADDRESS   (PERIPH_BASE + BDCR_OFFSET)
#define RCC_OFFSET   (RCC_BASE - PERIPH_BASE)
#define CR_OFFSET   (RCC_OFFSET + 0x00)
#define HSION_BitNumber   0x00
#define CR_HSION_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
#define MSION_BitNumber   0x08
#define CR_MSION_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MSION_BitNumber * 4))

Referenced by RCC_MSICmd().

#define PLLON_BitNumber   0x18
#define CR_PLLON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
#define CSSON_BitNumber   0x1C
#define CR_CSSON_BB   (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
#define CSR_OFFSET   (RCC_OFFSET + 0x34)
#define LSION_BitNumber   0x00
#define CSR_LSION_BB   (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
#define RTCEN_BitNumber   0x16
#define CSR_RTCEN_BB   (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCEN_BitNumber * 4))
#define RTCRST_BitNumber   0x17
#define CSR_RTCRST_BB   (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (RTCRST_BitNumber * 4))

Referenced by RCC_RTCResetCmd().

#define FLAG_MASK   ((uint8_t)0x1F)
#define CR_BYTE3_ADDRESS   ((uint32_t)0x40023802)
#define ICSCR_BYTE4_ADDRESS   ((uint32_t)0x40023807)

Referenced by RCC_AdjustMSICalibrationValue().

#define CFGR_BYTE3_ADDRESS   ((uint32_t)0x4002380A)

Referenced by RCC_PLLConfig().

#define CFGR_BYTE4_ADDRESS   ((uint32_t)0x4002380B)

Referenced by RCC_MCOConfig().

#define CIR_BYTE2_ADDRESS   ((uint32_t)0x4002380D)
#define CIR_BYTE3_ADDRESS   ((uint32_t)0x4002380E)
#define CSR_BYTE2_ADDRESS   ((uint32_t)0x40023835)

Function Documentation

void RCC_DeInit ( void  )

Resets the RCC clock configuration to the default reset state.

Parameters:
None
Return values:
None
Note:
The default reset state of the clock configuration is given below:
  • HSI ON and used as system clock source
  • HSE, PLL and PLLI2S OFF
  • AHB, APB1 and APB2 prescaler set to 1.
  • CSS, MCO1 and MCO2 OFF
  • All interrupts disabled
This function doesn't modify the configuration of the
  • Peripheral clocks
  • LSI, LSE and RTC clocks
Parameters:
None
Return values:
None
Note:
- The default reset state of the clock configuration is given below:
  • MSI ON and used as system clock source (MSI range is not modified by this function, it keep the value configured by user application)
  • HSI, HSE and PLL OFF
  • AHB, APB1 and APB2 prescaler set to 1.
  • CSS and MCO OFF
  • All interrupts disabled
  • However, this function doesn't modify the configuration of the
    • Peripheral clocks
    • LSI, LSE and RTC clocks
      Parameters:
      None
      Return values:
      None

References RCC.

ErrorStatus RCC_WaitForHSEStartUp ( void  )

Waits for HSE start-up.

Parameters:
None
Return values:
AnErrorStatus enumuration value:
  • SUCCESS: HSE oscillator is stable and ready to use
  • ERROR: HSE oscillator not yet ready
Note:
This functions waits on HSERDY flag to be set and return SUCCESS if this flag is set, otherwise returns ERROR if the timeout is reached and this flag is not set. The timeout value is defined by the constant HSE_STARTUP_TIMEOUT in stm32f2xx.h file. You can tailor it depending on the HSE crystal used in your application.
Parameters:
None
Return values:
AnErrorStatus enumeration value:
  • SUCCESS: HSE oscillator is stable and ready to use
  • ERROR: HSE oscillator not yet ready
Note:
This functions waits on HSERDY flag to be set and return SUCCESS if this flag is set, otherwise returns ERROR if the timeout is reached and this flag is not set. The timeout value is defined by the constant HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending on the HSE crystal used in your application.
Parameters:
None
Return values:
AnErrorStatus enumeration value:
  • SUCCESS: HSE oscillator is stable and ready to use
  • ERROR: HSE oscillator not yet ready
Note:
This functions waits on HSERDY flag to be set and return SUCCESS if this flag is set, otherwise returns ERROR if the timeout is reached and this flag is not set. The timeout value is defined by the constant HSE_STARTUP_TIMEOUT in stm32l1xx.h file. You can tailor it depending on the HSE crystal used in your application.
Parameters:
None
Return values:
AnErrorStatus enumeration value:
  • SUCCESS: HSE oscillator is stable and ready to use
  • ERROR: HSE oscillator not yet ready

References __IO, ERROR, HSE_STARTUP_TIMEOUT, RCC_FLAG_HSERDY, RCC_GetFlagStatus(), RESET, and SUCCESS.

Here is the call graph for this function:

void RCC_AdjustHSICalibrationValue ( uint8_t  HSICalibrationValue)

Adjusts the Internal High Speed oscillator (HSI) calibration value.

Parameters:
HSICalibrationValue,:specifies the calibration trimming value. This parameter must be a number between 0 and 0x1F.
Return values:
None
Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC.
Parameters:
HSICalibrationValue,:specifies the calibration trimming value. This parameter must be a number between 0 and 0x1F.
Return values:
None
Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal HSI RC. Refer to the Application Note AN3300 for more details on how to calibrate the HSI.
Parameters:
HSICalibrationValue,:specifies the HSI calibration trimming value. This parameter must be a number between 0 and 0x1F.
Return values:
None

References assert_param, CR_HSITRIM_Mask, IS_RCC_CALIBRATION_VALUE, RCC, and RCC_CR_HSITRIM.

void RCC_HSICmd ( FunctionalState  NewState)

Enables or disables the Internal High Speed oscillator (HSI).

Note:
HSI can not be stopped if it is used directly or through the PLL as system clock.
Parameters:
NewState,:new state of the HSI. This parameter can be: ENABLE or DISABLE.
Return values:
None
Note:
The HSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
HSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the HSI.
After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used as system clock source.
Parameters:
NewState,:new state of the HSI. This parameter can be: ENABLE or DISABLE.
Note:
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.
Return values:
None
Note:
- After enabling the HSI, the application software should wait on HSIRDY flag to be set indicating that HSI clock is stable and can be used to clock the PLL and/or system clock.
  • HSI can not be stopped if it is used directly or through the PLL as system clock. In this case, you have to select another source of the system clock then stop the HSI.
  • The HSI is stopped by hardware when entering STOP and STANDBY modes.
Parameters:
NewState,:new state of the HSI. This parameter can be: ENABLE or DISABLE.
Note:
When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator clock cycles.
Return values:
None

References __IO, assert_param, CR_HSION_BB, and IS_FUNCTIONAL_STATE.

void RCC_LSEConfig ( uint8_t  RCC_LSE)

Configures the External Low Speed oscillator (LSE).

Parameters:
RCC_LSE,:specifies the new state of the LSE. This parameter can be one of the following values:
  • RCC_LSE_OFF: LSE oscillator OFF
  • RCC_LSE_ON: LSE oscillator ON
  • RCC_LSE_Bypass: LSE oscillator bypassed with external clock
Return values:
None
Note:
As the LSE is in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the LSE (to be done once after reset).
After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
Parameters:
RCC_LSE,:specifies the new state of the LSE. This parameter can be one of the following values:
  • RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
  • RCC_LSE_ON: turn ON the LSE oscillator
  • RCC_LSE_Bypass: LSE oscillator bypassed with external clock
Return values:
None
Note:
- As the LSE is in the RTC domain and write access is denied to this domain after reset, you have to enable write access using PWR_RTCAccessCmd(ENABLE) function before to configure the LSE (to be done once after reset).
  • After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application software should wait on LSERDY flag to be set indicating that LSE clock is stable and can be used to clock the RTC.
Parameters:
RCC_LSE,:specifies the new state of the LSE. This parameter can be one of the following values:
  • RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after 6 LSE oscillator clock cycles.
  • RCC_LSE_ON: turn ON the LSE oscillator
  • RCC_LSE_Bypass: LSE oscillator bypassed with external clock
Return values:
None

References __IO, assert_param, BDCR_ADDRESS, IS_RCC_LSE, RCC_LSE_Bypass, RCC_LSE_OFF, and RCC_LSE_ON.

void RCC_LSICmd ( FunctionalState  NewState)

Enables or disables the Internal Low Speed oscillator (LSI).

Note:
LSI can not be disabled if the IWDG is running.
Parameters:
NewState,:new state of the LSI. This parameter can be: ENABLE or DISABLE.
Return values:
None
Note:
After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.
LSI can not be disabled if the IWDG is running.
Parameters:
NewState,:new state of the LSI. This parameter can be: ENABLE or DISABLE.
Note:
When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.
Return values:
None
Note:
- After enabling the LSI, the application software should wait on LSIRDY flag to be set indicating that LSI clock is stable and can be used to clock the IWDG and/or the RTC.
  • LSI can not be disabled if the IWDG is running.
Parameters:
NewState,:new state of the LSI. This parameter can be: ENABLE or DISABLE.
Note:
When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator clock cycles.
Return values:
None

References __IO, assert_param, CSR_LSION_BB, and IS_FUNCTIONAL_STATE.

void RCC_PLLCmd ( FunctionalState  NewState)

Enables or disables the PLL.

Note:
The PLL can not be disabled if it is used as system clock.
Parameters:
NewState,:new state of the PLL. This parameter can be: ENABLE or DISABLE.
Return values:
NoneEnables or disables the PLL.
Note:
After enabling the main PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
The main PLL can not be disabled if it is used as system clock source
The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Parameters:
NewState,:new state of the main PLL. This parameter can be: ENABLE or DISABLE.
Return values:
None
Note:
- After enabling the PLL, the application software should wait on PLLRDY flag to be set indicating that PLL clock is stable and can be used as system clock source.
  • The PLL can not be disabled if it is used as system clock source
  • The PLL is disabled by hardware when entering STOP and STANDBY modes.
Parameters:
NewState,:new state of the PLL. This parameter can be: ENABLE or DISABLE.
Return values:
None

References __IO, assert_param, CR_PLLON_BB, and IS_FUNCTIONAL_STATE.

void RCC_ClockSecuritySystemCmd ( FunctionalState  NewState)

Enables or disables the Clock Security System.

Parameters:
NewState,:new state of the Clock Security System.. This parameter can be: ENABLE or DISABLE.
Return values:
None
Note:
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.
Parameters:
NewState,:new state of the Clock Security System. This parameter can be: ENABLE or DISABLE.
Return values:
None
Note:
If a failure is detected on the HSE oscillator clock, this oscillator is automatically disabled and an interrupt is generated to inform the software about the failure (Clock Security System Interrupt, CSSI), allowing the MCU to perform rescue operations. The CSSI is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
Parameters:
NewState,:new state of the Clock Security System. This parameter can be: ENABLE or DISABLE.
Return values:
None

References __IO, assert_param, CR_CSSON_BB, and IS_FUNCTIONAL_STATE.

void RCC_SYSCLKConfig ( uint32_t  RCC_SYSCLKSource)

Configures the system clock (SYSCLK).

Parameters:
RCC_SYSCLKSource,:specifies the clock source used as system clock. This parameter can be one of the following values:
  • RCC_SYSCLKSource_HSI: HSI selected as system clock
  • RCC_SYSCLKSource_HSE: HSE selected as system clock
  • RCC_SYSCLKSource_PLLCLK: PLL selected as system clock
Return values:
None
Note:
The HSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use RCC_GetSYSCLKSource() function to know which clock is currently used as system clock source.
Parameters:
RCC_SYSCLKSource,:specifies the clock source used as system clock. This parameter can be one of the following values:
  • RCC_SYSCLKSource_HSI: HSI selected as system clock source
  • RCC_SYSCLKSource_HSE: HSE selected as system clock source
  • RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
Return values:
None
Note:
- The MSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
  • A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use RCC_GetSYSCLKSource() function to know which clock is currently used as system clock source.
Parameters:
RCC_SYSCLKSource,:specifies the clock source used as system clock source This parameter can be one of the following values:
  • RCC_SYSCLKSource_MSI: MSI selected as system clock source
  • RCC_SYSCLKSource_HSI: HSI selected as system clock source
  • RCC_SYSCLKSource_HSE: HSE selected as system clock source
  • RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
Return values:
None

References assert_param, CFGR_SW_Mask, IS_RCC_SYSCLK_SOURCE, RCC, and RCC_CFGR_SW.

uint8_t RCC_GetSYSCLKSource ( void  )

Returns the clock source used as system clock.

Parameters:
None
Return values:
Theclock source used as system clock. The returned value can be one of the following:
  • 0x00: HSI used as system clock
  • 0x04: HSE used as system clock
  • 0x08: PLL used as system clock
Parameters:
None
Return values:
Theclock source used as system clock. The returned value can be one of the following:
  • 0x00: HSI used as system clock
  • 0x04: HSE used as system clock
  • 0x08: PLL used as system clock
Parameters:
None
Return values:
Theclock source used as system clock. The returned value can be one of the following values:
  • 0x00: MSI used as system clock
  • 0x04: HSI used as system clock
  • 0x08: HSE used as system clock
  • 0x0C: PLL used as system clock

References CFGR_SWS_Mask, RCC, and RCC_CFGR_SWS.

void RCC_HCLKConfig ( uint32_t  RCC_SYSCLK)

Configures the AHB clock (HCLK).

Parameters:
RCC_SYSCLK,:defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:
  • RCC_SYSCLK_Div1: AHB clock = SYSCLK
  • RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
  • RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
  • RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
  • RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
  • RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
  • RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
  • RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
  • RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
Return values:
None
Note:
Depending on the device voltage range, the software has to set correctly these bits to ensure that HCLK not exceed the maximum allowed frequency (for more details refer to section above "CPU, AHB and APB busses clocks configuration functions")
Parameters:
RCC_SYSCLK,:defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:
  • RCC_SYSCLK_Div1: AHB clock = SYSCLK
  • RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
  • RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
  • RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
  • RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
  • RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
  • RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
  • RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
  • RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
Return values:
None
Note:
Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details refer to section above "CPU, AHB and APB busses clocks configuration functions")
Parameters:
RCC_SYSCLK,:defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:
  • RCC_SYSCLK_Div1: AHB clock = SYSCLK
  • RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
  • RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
  • RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
  • RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
  • RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
  • RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
  • RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
  • RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
Return values:
None

References assert_param, CFGR_HPRE_Reset_Mask, IS_RCC_HCLK, RCC, and RCC_CFGR_HPRE.

void RCC_PCLK1Config ( uint32_t  RCC_HCLK)

Configures the Low Speed APB clock (PCLK1).

Parameters:
RCC_HCLK,:defines the APB1 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:
  • RCC_HCLK_Div1: APB1 clock = HCLK
  • RCC_HCLK_Div2: APB1 clock = HCLK/2
  • RCC_HCLK_Div4: APB1 clock = HCLK/4
  • RCC_HCLK_Div8: APB1 clock = HCLK/8
  • RCC_HCLK_Div16: APB1 clock = HCLK/16
Return values:
None

References assert_param, CFGR_PPRE1_Reset_Mask, IS_RCC_PCLK, RCC, and RCC_CFGR_PPRE1.

void RCC_PCLK2Config ( uint32_t  RCC_HCLK)

Configures the High Speed APB clock (PCLK2).

Parameters:
RCC_HCLK,:defines the APB2 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:
  • RCC_HCLK_Div1: APB2 clock = HCLK
  • RCC_HCLK_Div2: APB2 clock = HCLK/2
  • RCC_HCLK_Div4: APB2 clock = HCLK/4
  • RCC_HCLK_Div8: APB2 clock = HCLK/8
  • RCC_HCLK_Div16: APB2 clock = HCLK/16
Return values:
None

References assert_param, CFGR_PPRE2_Reset_Mask, IS_RCC_PCLK, RCC, and RCC_CFGR_PPRE2.

void RCC_GetClocksFreq ( RCC_ClocksTypeDef *  RCC_Clocks)

Returns the frequencies of different on chip clocks.

Parameters:
RCC_Clocks,:pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.
Return values:
NoneReturns the frequencies of different on chip clocks.

Returns the frequencies of the System, AHB and APB busses clocks.

Note:
The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.
(*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.
(**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be not correct when using fractional value for HSE crystal.
Parameters:
RCC_Clocks,:pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.
Note:
This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.
Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update the structure's field. Otherwise, any configuration based on this function will be incorrect.
Return values:
None
Note:
The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.
(*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.
(**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
The result of this function could be not correct when using fractional value for HSE crystal.
Parameters:
RCC_Clocks,:pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.
Note:
This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.
Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update the structure's field. Otherwise, any configuration based on this function will be incorrect.
Return values:
None
Note:
- The frequency returned by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the source selected by RCC_SYSCLKConfig():
  • If SYSCLK source is MSI, function returns constant the MSI value as defined by the MSI range, refer to RCC_MSIRangeConfig()
  • If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
  • If SYSCLK source is HSE, function returns constant HSE_VALUE(**)

(*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().

(**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may return wrong result.

  • The result of this function could be not correct when using fractional value for HSE crystal.
Parameters:
RCC_Clocks,:pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies.
Return values:
None

References RCC_ClocksTypeDef::ADCCLK_Frequency, CFGR_ADCPRE_Set_Mask, CFGR_HPRE_Set_Mask, CFGR_PLLMull_Mask, CFGR_PLLSRC_Mask, CFGR_PLLXTPRE_Mask, CFGR_PPRE1_Set_Mask, CFGR_PPRE2_Set_Mask, CFGR_SWS_Mask, RCC_ClocksTypeDef::HCLK_Frequency, HSE_VALUE, HSI_VALUE, RCC_ClocksTypeDef::PCLK1_Frequency, RCC_ClocksTypeDef::PCLK2_Frequency, RCC, RCC_CFGR_HPRE, RCC_CFGR_PPRE1, RCC_CFGR_PPRE2, RCC_CFGR_SWS, RCC_PLLCFGR_PLLM, RCC_PLLCFGR_PLLN, RCC_PLLCFGR_PLLP, RCC_PLLCFGR_PLLSRC, RESET, and RCC_ClocksTypeDef::SYSCLK_Frequency.

void RCC_RTCCLKConfig ( uint32_t  RCC_RTCCLKSource)

Configures the RTC clock (RTCCLK).

Note:
Once the RTC clock is selected it can’t be changed unless the Backup domain is reset.
Parameters:
RCC_RTCCLKSource,:specifies the RTC clock source. This parameter can be one of the following values:
  • RCC_RTCCLKSource_LSE: LSE selected as RTC clock
  • RCC_RTCCLKSource_LSI: LSI selected as RTC clock
  • RCC_RTCCLKSource_HSE_Div128: HSE clock divided by 128 selected as RTC clock
Return values:
NoneConfigures the RTC and LCD clock (RTCCLK / LCDCLK).
Note:
As the RTC clock configuration bits are in the Backup domain and write access is denied to this domain after reset, you have to enable write access using PWR_BackupAccessCmd(ENABLE) function before to configure the RTC clock source (to be done once after reset).
Once the RTC clock is configured it can't be changed unless the Backup domain is reset using RCC_BackupResetCmd() function, or by a Power On Reset (POR).
Parameters:
RCC_RTCCLKSource,:specifies the RTC clock source. This parameter can be one of the following values:
  • RCC_RTCCLKSource_LSE: LSE selected as RTC clock
  • RCC_RTCCLKSource_LSI: LSI selected as RTC clock
  • RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected as RTC clock, where x:[2,31]
Note:
If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).
Return values:
None
Note:
- As the RTC clock configuration bits are in the RTC domain and write access is denied to this domain after reset, you have to enable write access using PWR_RTCAccessCmd(ENABLE) function before to configure the RTC clock source (to be done once after reset).
  • Once the RTC clock is configured it can't be changed unless the RTC is reset using RCC_RTCResetCmd function, or by a Power On Reset (POR)
  • The RTC clock (RTCCLK) is used also to clock the LCD (LCDCLK).
Parameters:
RCC_RTCCLKSource,:specifies the RTC clock source. This parameter can be one of the following values:
  • RCC_RTCCLKSource_LSE: LSE selected as RTC clock
  • RCC_RTCCLKSource_LSI: LSI selected as RTC clock
  • RCC_RTCCLKSource_HSE_Div2: HSE divided by 2 selected as RTC clock
  • RCC_RTCCLKSource_HSE_Div4: HSE divided by 4 selected as RTC clock
  • RCC_RTCCLKSource_HSE_Div8: HSE divided by 8 selected as RTC clock
  • RCC_RTCCLKSource_HSE_Div16: HSE divided by 16 selected as RTC clock
Note:
- If the LSE or LSI is used as RTC clock source, the RTC continues to work in STOP and STANDBY modes, and can be used as wakeup source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in STOP and STANDBY modes.
  • The maximum input clock frequency for RTC is 1MHz (when using HSE as RTC clock source).
Return values:
None

References assert_param, IS_RCC_RTCCLK_SOURCE, RCC, and RCC_CFGR_RTCPRE.

void RCC_RTCCLKCmd ( FunctionalState  NewState)

Enables or disables the RTC clock.

Note:
This function must be used only after the RTC clock was selected using the RCC_RTCCLKConfig function.
Parameters:
NewState,:new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
Return values:
None
Note:
This function must be used only after the RTC clock source was selected using the RCC_RTCCLKConfig function.
Parameters:
NewState,:new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

References __IO, assert_param, BDCR_RTCEN_BB, and IS_FUNCTIONAL_STATE.

void RCC_BackupResetCmd ( FunctionalState  NewState)

Forces or releases the Backup domain reset.

Parameters:
NewState,:new state of the Backup domain reset. This parameter can be: ENABLE or DISABLE.
Return values:
None
Note:
This function resets the RTC peripheral (including the backup registers) and the RTC clock source selection in RCC_CSR register.
The BKPSRAM is not affected by this reset.
Parameters:
NewState,:new state of the Backup domain reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

References __IO, assert_param, BDCR_BDRST_BB, and IS_FUNCTIONAL_STATE.

void RCC_APB1PeriphClockCmd ( uint32_t  RCC_APB1Periph,
FunctionalState  NewState 
)

Enables or disables the Low Speed APB (APB1) peripheral clock.

Parameters:
RCC_APB1Periph,:specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None
Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters:
RCC_APB1Periph,:specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB1Periph_TIM2: TIM2 clock
  • RCC_APB1Periph_TIM3: TIM3 clock
  • RCC_APB1Periph_TIM4: TIM4 clock
  • RCC_APB1Periph_TIM5: TIM5 clock
  • RCC_APB1Periph_TIM6: TIM6 clock
  • RCC_APB1Periph_TIM7: TIM7 clock
  • RCC_APB1Periph_TIM12: TIM12 clock
  • RCC_APB1Periph_TIM13: TIM13 clock
  • RCC_APB1Periph_TIM14: TIM14 clock
  • RCC_APB1Periph_WWDG: WWDG clock
  • RCC_APB1Periph_SPI2: SPI2 clock
  • RCC_APB1Periph_SPI3: SPI3 clock
  • RCC_APB1Periph_USART2: USART2 clock
  • RCC_APB1Periph_USART3: USART3 clock
  • RCC_APB1Periph_UART4: UART4 clock
  • RCC_APB1Periph_UART5: UART5 clock
  • RCC_APB1Periph_I2C1: I2C1 clock
  • RCC_APB1Periph_I2C2: I2C2 clock
  • RCC_APB1Periph_I2C3: I2C3 clock
  • RCC_APB1Periph_CAN1: CAN1 clock
  • RCC_APB1Periph_CAN2: CAN2 clock
  • RCC_APB1Periph_PWR: PWR clock
  • RCC_APB1Periph_DAC: DAC clock
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None
Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters:
RCC_APB1Periph,:specifies the APB1 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB1Periph_TIM2
  • RCC_APB1Periph_TIM3
  • RCC_APB1Periph_TIM4
  • RCC_APB1Periph_TIM6
  • RCC_APB1Periph_TIM7
  • RCC_APB1Periph_LCD
  • RCC_APB1Periph_WWDG
  • RCC_APB1Periph_SPI2
  • RCC_APB1Periph_USART2
  • RCC_APB1Periph_USART3
  • RCC_APB1Periph_I2C1
  • RCC_APB1Periph_I2C2
  • RCC_APB1Periph_USB
  • RCC_APB1Periph_PWR
  • RCC_APB1Periph_DAC
  • RCC_APB1Periph_COMP
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB1_PERIPH, and RCC.

void RCC_APB2PeriphClockCmd ( uint32_t  RCC_APB2Periph,
FunctionalState  NewState 
)

Enables or disables the High Speed APB (APB2) peripheral clock.

Parameters:
RCC_APB2Periph,:specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None
Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters:
RCC_APB2Periph,:specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB2Periph_TIM1: TIM1 clock
  • RCC_APB2Periph_TIM8: TIM8 clock
  • RCC_APB2Periph_USART1: USART1 clock
  • RCC_APB2Periph_USART6: USART6 clock
  • RCC_APB2Periph_ADC1: ADC1 clock
  • RCC_APB2Periph_ADC2: ADC2 clock
  • RCC_APB2Periph_ADC3: ADC3 clock
  • RCC_APB2Periph_SDIO: SDIO clock
  • RCC_APB2Periph_SPI1: SPI1 clock
  • RCC_APB2Periph_SYSCFG: SYSCFG clock
  • RCC_APB2Periph_TIM9: TIM9 clock
  • RCC_APB2Periph_TIM10: TIM10 clock
  • RCC_APB2Periph_TIM11: TIM11 clock
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None
Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters:
RCC_APB2Periph,:specifies the APB2 peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_APB2Periph_SYSCFG
  • RCC_APB2Periph_TIM9
  • RCC_APB2Periph_TIM10
  • RCC_APB2Periph_TIM11
  • RCC_APB2Periph_ADC1
  • RCC_APB2Periph_SPI1
  • RCC_APB2Periph_USART1
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB2_PERIPH, and RCC.

void RCC_APB1PeriphResetCmd ( uint32_t  RCC_APB1Periph,
FunctionalState  NewState 
)

Forces or releases Low Speed APB (APB1) peripheral reset.

Parameters:
RCC_APB1Periph,:specifies the APB1 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_APB1Periph_TIM2, RCC_APB1Periph_TIM3, RCC_APB1Periph_TIM4, RCC_APB1Periph_TIM5, RCC_APB1Periph_TIM6, RCC_APB1Periph_TIM7, RCC_APB1Periph_WWDG, RCC_APB1Periph_SPI2, RCC_APB1Periph_SPI3, RCC_APB1Periph_USART2, RCC_APB1Periph_USART3, RCC_APB1Periph_USART4, RCC_APB1Periph_USART5, RCC_APB1Periph_I2C1, RCC_APB1Periph_I2C2, RCC_APB1Periph_USB, RCC_APB1Periph_CAN1, RCC_APB1Periph_BKP, RCC_APB1Periph_PWR, RCC_APB1Periph_DAC, RCC_APB1Periph_CEC, RCC_APB1Periph_TIM12, RCC_APB1Periph_TIM13, RCC_APB1Periph_TIM14
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None
Parameters:
RCC_APB1Periph,:specifies the APB1 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_APB1Periph_TIM2: TIM2 clock
  • RCC_APB1Periph_TIM3: TIM3 clock
  • RCC_APB1Periph_TIM4: TIM4 clock
  • RCC_APB1Periph_TIM5: TIM5 clock
  • RCC_APB1Periph_TIM6: TIM6 clock
  • RCC_APB1Periph_TIM7: TIM7 clock
  • RCC_APB1Periph_TIM12: TIM12 clock
  • RCC_APB1Periph_TIM13: TIM13 clock
  • RCC_APB1Periph_TIM14: TIM14 clock
  • RCC_APB1Periph_WWDG: WWDG clock
  • RCC_APB1Periph_SPI2: SPI2 clock
  • RCC_APB1Periph_SPI3: SPI3 clock
  • RCC_APB1Periph_USART2: USART2 clock
  • RCC_APB1Periph_USART3: USART3 clock
  • RCC_APB1Periph_UART4: UART4 clock
  • RCC_APB1Periph_UART5: UART5 clock
  • RCC_APB1Periph_I2C1: I2C1 clock
  • RCC_APB1Periph_I2C2: I2C2 clock
  • RCC_APB1Periph_I2C3: I2C3 clock
  • RCC_APB1Periph_CAN1: CAN1 clock
  • RCC_APB1Periph_CAN2: CAN2 clock
  • RCC_APB1Periph_PWR: PWR clock
  • RCC_APB1Periph_DAC: DAC clock
NewState,:new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values:
None
Parameters:
RCC_APB1Periph,:specifies the APB1 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_APB1Periph_TIM2
  • RCC_APB1Periph_TIM3
  • RCC_APB1Periph_TIM4
  • RCC_APB1Periph_TIM6
  • RCC_APB1Periph_TIM7
  • RCC_APB1Periph_LCD
  • RCC_APB1Periph_WWDG
  • RCC_APB1Periph_SPI2
  • RCC_APB1Periph_USART2
  • RCC_APB1Periph_USART3
  • RCC_APB1Periph_I2C1
  • RCC_APB1Periph_I2C2
  • RCC_APB1Periph_USB
  • RCC_APB1Periph_PWR
  • RCC_APB1Periph_DAC
  • RCC_APB1Periph_COMP
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB1_PERIPH, and RCC.

void RCC_APB2PeriphResetCmd ( uint32_t  RCC_APB2Periph,
FunctionalState  NewState 
)

Forces or releases High Speed APB (APB2) peripheral reset.

Parameters:
RCC_APB2Periph,:specifies the APB2 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_APB2Periph_AFIO, RCC_APB2Periph_GPIOA, RCC_APB2Periph_GPIOB, RCC_APB2Periph_GPIOC, RCC_APB2Periph_GPIOD, RCC_APB2Periph_GPIOE, RCC_APB2Periph_GPIOF, RCC_APB2Periph_GPIOG, RCC_APB2Periph_ADC1, RCC_APB2Periph_ADC2, RCC_APB2Periph_TIM1, RCC_APB2Periph_SPI1, RCC_APB2Periph_TIM8, RCC_APB2Periph_USART1, RCC_APB2Periph_ADC3, RCC_APB2Periph_TIM15, RCC_APB2Periph_TIM16, RCC_APB2Periph_TIM17, RCC_APB2Periph_TIM9, RCC_APB2Periph_TIM10, RCC_APB2Periph_TIM11
NewState,:new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values:
None
Parameters:
RCC_APB2Periph,:specifies the APB2 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_APB2Periph_TIM1: TIM1 clock
  • RCC_APB2Periph_TIM8: TIM8 clock
  • RCC_APB2Periph_USART1: USART1 clock
  • RCC_APB2Periph_USART6: USART6 clock
  • RCC_APB2Periph_ADC1: ADC1 clock
  • RCC_APB2Periph_ADC2: ADC2 clock
  • RCC_APB2Periph_ADC3: ADC3 clock
  • RCC_APB2Periph_SDIO: SDIO clock
  • RCC_APB2Periph_SPI1: SPI1 clock
  • RCC_APB2Periph_SYSCFG: SYSCFG clock
  • RCC_APB2Periph_TIM9: TIM9 clock
  • RCC_APB2Periph_TIM10: TIM10 clock
  • RCC_APB2Periph_TIM11: TIM11 clock
NewState,:new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values:
None
Parameters:
RCC_APB2Periph,:specifies the APB2 peripheral to reset. This parameter can be any combination of the following values:
  • RCC_APB2Periph_SYSCFG
  • RCC_APB2Periph_TIM9
  • RCC_APB2Periph_TIM10
  • RCC_APB2Periph_TIM11
  • RCC_APB2Periph_ADC1
  • RCC_APB2Periph_SPI1
  • RCC_APB2Periph_USART1
NewState,:new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_APB2_PERIPH, IS_RCC_APB2_RESET_PERIPH, and RCC.

void RCC_ITConfig ( uint8_t  RCC_IT,
FunctionalState  NewState 
)

Enables or disables the specified RCC interrupts.

Parameters:
RCC_IT,:specifies the RCC interrupt sources to be enabled or disabled.

For STM32_Connectivity_line_devices, this parameter can be any combination of the following values

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt

For other_STM32_devices, this parameter can be any combination of the following values

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
Parameters:
NewState,:new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None
Parameters:
RCC_IT,:specifies the RCC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: main PLL ready interrupt
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
NewState,:new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None
Note:
The CSS interrupt doesn't have an enable bit; once the CSS is enabled and if the HSE clock fails, the CSS interrupt occurs and an NMI is automatically generated. The NMI will be executed indefinitely, and since NMI has higher priority than any other IRQ (and main program) the application will be stacked in the NMI ISR unless the CSS interrupt pending bit is cleared.
Parameters:
RCC_IT,:specifies the RCC interrupt sources to be enabled or disabled. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_MSIRDY: MSI ready interrupt
NewState,:new state of the specified RCC interrupts. This parameter can be: ENABLE or DISABLE.
Return values:
None

References __IO, assert_param, CIR_BYTE2_ADDRESS, DISABLE, IS_FUNCTIONAL_STATE, and IS_RCC_IT.

FlagStatus RCC_GetFlagStatus ( uint8_t  RCC_FLAG)

Checks whether the specified RCC flag is set or not.

Parameters:
RCC_FLAG,:specifies the flag to check.

For STM32_Connectivity_line_devices, this parameter can be one of the following values:

  • RCC_FLAG_HSIRDY: HSI oscillator clock ready
  • RCC_FLAG_HSERDY: HSE oscillator clock ready
  • RCC_FLAG_PLLRDY: PLL clock ready
  • RCC_FLAG_PLL2RDY: PLL2 clock ready
  • RCC_FLAG_PLL3RDY: PLL3 clock ready
  • RCC_FLAG_LSERDY: LSE oscillator clock ready
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready
  • RCC_FLAG_PINRST: Pin reset
  • RCC_FLAG_PORRST: POR/PDR reset
  • RCC_FLAG_SFTRST: Software reset
  • RCC_FLAG_IWDGRST: Independent Watchdog reset
  • RCC_FLAG_WWDGRST: Window Watchdog reset
  • RCC_FLAG_LPWRRST: Low Power reset

For other_STM32_devices, this parameter can be one of the following values:

  • RCC_FLAG_HSIRDY: HSI oscillator clock ready
  • RCC_FLAG_HSERDY: HSE oscillator clock ready
  • RCC_FLAG_PLLRDY: PLL clock ready
  • RCC_FLAG_LSERDY: LSE oscillator clock ready
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready
  • RCC_FLAG_PINRST: Pin reset
  • RCC_FLAG_PORRST: POR/PDR reset
  • RCC_FLAG_SFTRST: Software reset
  • RCC_FLAG_IWDGRST: Independent Watchdog reset
  • RCC_FLAG_WWDGRST: Window Watchdog reset
  • RCC_FLAG_LPWRRST: Low Power reset
Return values:
Thenew state of RCC_FLAG (SET or RESET).
Parameters:
RCC_FLAG,:specifies the flag to check. This parameter can be one of the following values:
  • RCC_FLAG_HSIRDY: HSI oscillator clock ready
  • RCC_FLAG_HSERDY: HSE oscillator clock ready
  • RCC_FLAG_PLLRDY: main PLL clock ready
  • RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
  • RCC_FLAG_LSERDY: LSE oscillator clock ready
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready
  • RCC_FLAG_BORRST: POR/PDR or BOR reset
  • RCC_FLAG_PINRST: Pin reset
  • RCC_FLAG_PORRST: POR/PDR reset
  • RCC_FLAG_SFTRST: Software reset
  • RCC_FLAG_IWDGRST: Independent Watchdog reset
  • RCC_FLAG_WWDGRST: Window Watchdog reset
  • RCC_FLAG_LPWRRST: Low Power reset
Return values:
Thenew state of RCC_FLAG (SET or RESET).
Parameters:
RCC_FLAG,:specifies the flag to check. This parameter can be one of the following values:
  • RCC_FLAG_HSIRDY: HSI oscillator clock ready
  • RCC_FLAG_MSIRDY: MSI oscillator clock ready
  • RCC_FLAG_HSERDY: HSE oscillator clock ready
  • RCC_FLAG_PLLRDY: PLL clock ready
  • RCC_FLAG_LSERDY: LSE oscillator clock ready
  • RCC_FLAG_LSIRDY: LSI oscillator clock ready
  • RCC_FLAG_OBLRST: Option Byte Loader (OBL) reset
  • RCC_FLAG_PINRST: Pin reset
  • RCC_FLAG_PORRST: POR/PDR reset
  • RCC_FLAG_SFTRST: Software reset
  • RCC_FLAG_IWDGRST: Independent Watchdog reset
  • RCC_FLAG_WWDGRST: Window Watchdog reset
  • RCC_FLAG_LPWRRST: Low Power reset
Return values:
Thenew state of RCC_FLAG (SET or RESET).

References assert_param, FLAG_MASK, FLAG_Mask, IS_RCC_FLAG, RCC, RESET, and SET.

void RCC_ClearFlag ( void  )

Clears the RCC reset flags.

Note:
The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
Parameters:
None
Return values:
NoneClears the RCC reset flags.

Clears the RCC reset flags. The reset flags are: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST.

Parameters:
None
Return values:
None

References CSR_RMVF_Set, RCC, and RCC_CSR_RMVF.

ITStatus RCC_GetITStatus ( uint8_t  RCC_IT)

Checks whether the specified RCC interrupt has occurred or not.

Parameters:
RCC_IT,:specifies the RCC interrupt source to check.

For STM32_Connectivity_line_devices, this parameter can be one of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt

For other_STM32_devices, this parameter can be one of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt
Return values:
Thenew state of RCC_IT (SET or RESET).
Parameters:
RCC_IT,:specifies the RCC interrupt source to check. This parameter can be one of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: main PLL ready interrupt
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt
Return values:
Thenew state of RCC_IT (SET or RESET).
Parameters:
RCC_IT,:specifies the RCC interrupt source to check. This parameter can be one of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_MSIRDY: MSI ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt
Return values:
Thenew state of RCC_IT (SET or RESET).

References assert_param, IS_RCC_GET_IT, RCC, RESET, and SET.

void RCC_ClearITPendingBit ( uint8_t  RCC_IT)

Clears the RCC’s interrupt pending bits.

Parameters:
RCC_IT,:specifies the interrupt pending bit to clear.

For STM32_Connectivity_line_devices, this parameter can be any combination of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_PLL2RDY: PLL2 ready interrupt
  • RCC_IT_PLL3RDY: PLL3 ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt

For other_STM32_devices, this parameter can be any combination of the following values:

  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt
    Return values:
    NoneClears the RCC’s interrupt pending bits.
    Parameters:
    RCC_IT,:specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: main PLL ready interrupt
  • RCC_IT_PLLI2SRDY: PLLI2S ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt
    Return values:
    None
    Parameters:
    RCC_IT,:specifies the interrupt pending bit to clear. This parameter can be any combination of the following values:
  • RCC_IT_LSIRDY: LSI ready interrupt
  • RCC_IT_LSERDY: LSE ready interrupt
  • RCC_IT_HSIRDY: HSI ready interrupt
  • RCC_IT_HSERDY: HSE ready interrupt
  • RCC_IT_PLLRDY: PLL ready interrupt
  • RCC_IT_MSIRDY: MSI ready interrupt
  • RCC_IT_CSS: Clock Security System interrupt
    Return values:
    None

References __IO, assert_param, CIR_BYTE3_ADDRESS, and IS_RCC_CLEAR_IT.

void RCC_MSIRangeConfig ( uint32_t  RCC_MSIRange)

Configures the Internal Multi Speed oscillator (MSI) clock range.

Note:
- After restart from Reset or wakeup from STANDBY, the MSI clock is around 2.097 MHz. The MSI clock does not change after wake-up from STOP mode.
  • The MSI clock range can be modified on the fly.
Parameters:
RCC_MSIRange,:specifies the MSI Clock range. This parameter must be one of the following values:
  • RCC_MSIRange_0: MSI clock is around 65.536 KHz
  • RCC_MSIRange_1: MSI clock is around 131.072 KHz
  • RCC_MSIRange_2: MSI clock is around 262.144 KHz
  • RCC_MSIRange_3: MSI clock is around 524.288 KHz
  • RCC_MSIRange_4: MSI clock is around 1.048 MHz
  • RCC_MSIRange_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
  • RCC_MSIRange_6: MSI clock is around
Return values:
None

References assert_param, IS_RCC_MSI_CLOCK_RANGE, RCC, and RCC_ICSCR_MSIRANGE.

void RCC_AdjustMSICalibrationValue ( uint8_t  MSICalibrationValue)

Adjusts the Internal Multi Speed oscillator (MSI) calibration value.

Note:
The calibration is used to compensate for the variations in voltage and temperature that influence the frequency of the internal MSI RC. Refer to the Application Note AN3300 for more details on how to calibrate the MSI.
Parameters:
MSICalibrationValue,:specifies the MSI calibration trimming value. This parameter must be a number between 0 and 0xFF.
Return values:
None

References __IO, assert_param, ICSCR_BYTE4_ADDRESS, and IS_RCC_MSI_CALIBRATION_VALUE.

void RCC_MSICmd ( FunctionalState  NewState)

Enables or disables the Internal Multi Speed oscillator (MSI).

Note:
- The MSI is stopped by hardware when entering STOP and STANDBY modes. It is used (enabled by hardware) as system clock source after startup from Reset, wakeup from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
  • MSI can not be stopped if it is used as system clock source. In this case, you have to select another source of the system clock then stop the MSI.
  • After enabling the MSI, the application software should wait on MSIRDY flag to be set indicating that MSI clock is stable and can be used as system clock source.
Parameters:
NewState,:new state of the MSI. This parameter can be: ENABLE or DISABLE.
Note:
When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator clock cycles.
Return values:
None

References __IO, assert_param, CR_MSION_BB, and IS_FUNCTIONAL_STATE.

void RCC_PLLConfig ( uint8_t  RCC_PLLSource,
uint8_t  RCC_PLLMul,
uint8_t  RCC_PLLDiv 
)

Configures the PLL clock source and multiplication factor.

Note:
This function must be used only when the PLL is disabled.
Parameters:
RCC_PLLSource,:specifies the PLL entry clock source. This parameter can be one of the following values:
  • RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock source
  • RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock source
Note:
The minimum input clock frequency for PLL is 2 MHz (when using HSE as PLL source).
Parameters:
RCC_PLLMul,:specifies the PLL multiplication factor, which drive the PLLVCO clock This parameter can be:
  • RCC_PLLMul_3: PLL clock source multiplied by 3
  • RCC_PLLMul_4: PLL clock source multiplied by 4
  • RCC_PLLMul_6: PLL clock source multiplied by 6
  • RCC_PLLMul_8: PLL clock source multiplied by 8
  • RCC_PLLMul_12: PLL clock source multiplied by 12
  • RCC_PLLMul_16: PLL clock source multiplied by 16
  • RCC_PLLMul_24: PLL clock source multiplied by 24
  • RCC_PLLMul_32: PLL clock source multiplied by 32
  • RCC_PLLMul_48: PLL clock source multiplied by 48
Note:
The application software must set correctly the PLL multiplication factor to avoid exceeding
  • 96 MHz as PLLVCO when the product is in range 1
  • 48 MHz as PLLVCO when the product is in range 2
  • 24 MHz when the product is in range 3
When using the USB the PLLVCO should be 96MHz
Parameters:
RCC_PLLDiv,:specifies the PLL division factor. This parameter can be:
  • RCC_PLLDiv_2: PLL Clock output divided by 2
  • RCC_PLLDiv_3: PLL Clock output divided by 3
  • RCC_PLLDiv_4: PLL Clock output divided by 4
Note:
The application software must set correctly the output division to avoid exceeding 32 MHz as SYSCLK.
Return values:
None

References __IO, assert_param, CFGR_BYTE3_ADDRESS, IS_RCC_PLL_DIV, IS_RCC_PLL_MUL, and IS_RCC_PLL_SOURCE.

void RCC_LSEClockSecuritySystemCmd ( FunctionalState  NewState)
void RCC_MCOConfig ( uint8_t  RCC_MCOSource,
uint8_t  RCC_MCODiv 
)

Selects the clock source to output on MCO pin (PA8).

Note:
PA8 should be configured in alternate function mode.
Parameters:
RCC_MCOSource,:specifies the clock source to output. This parameter can be one of the following values:
  • RCC_MCOSource_NoClock: No clock selected
  • RCC_MCOSource_SYSCLK: System clock selected
  • RCC_MCOSource_HSI: HSI oscillator clock selected
  • RCC_MCOSource_MSI: MSI oscillator clock selected
  • RCC_MCOSource_HSE: HSE oscillator clock selected
  • RCC_MCOSource_PLLCLK: PLL clock selected
  • RCC_MCOSource_LSI: LSI clock selected
  • RCC_MCOSource_LSE: LSE clock selected
RCC_MCODiv,:specifies the MCO prescaler. This parameter can be one of the following values:
  • RCC_MCODiv_1: no division applied to MCO clock
  • RCC_MCODiv_2: division by 2 applied to MCO clock
  • RCC_MCODiv_4: division by 4 applied to MCO clock
  • RCC_MCODiv_8: division by 8 applied to MCO clock
  • RCC_MCODiv_16: division by 16 applied to MCO clock
Return values:
None

References __IO, assert_param, CFGR_BYTE4_ADDRESS, IS_RCC_MCO_DIV, and IS_RCC_MCO_SOURCE.

void RCC_RTCResetCmd ( FunctionalState  NewState)

Forces or releases the RTC peripheral and associated resources reset.

Note:
This function resets the RTC peripheral, RTC clock source selection (in RCC_CSR) and the backup registers.
Parameters:
NewState,:new state of the RTC reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

References __IO, assert_param, CSR_RTCRST_BB, and IS_FUNCTIONAL_STATE.

void RCC_AHBPeriphClockCmd ( uint32_t  RCC_AHBPeriph,
FunctionalState  NewState 
)

Enables or disables the AHB peripheral clock.

Parameters:
RCC_AHBPeriph,:specifies the AHB peripheral to gates its clock.

For STM32_Connectivity_line_devices, this parameter can be any combination of the following values:

  • RCC_AHBPeriph_DMA1
  • RCC_AHBPeriph_DMA2
  • RCC_AHBPeriph_SRAM
  • RCC_AHBPeriph_FLITF
  • RCC_AHBPeriph_CRC
  • RCC_AHBPeriph_OTG_FS
  • RCC_AHBPeriph_ETH_MAC
  • RCC_AHBPeriph_ETH_MAC_Tx
  • RCC_AHBPeriph_ETH_MAC_Rx

For other_STM32_devices, this parameter can be any combination of the following values:

  • RCC_AHBPeriph_DMA1
  • RCC_AHBPeriph_DMA2
  • RCC_AHBPeriph_SRAM
  • RCC_AHBPeriph_FLITF
  • RCC_AHBPeriph_CRC
  • RCC_AHBPeriph_FSMC
  • RCC_AHBPeriph_SDIO
Note:
SRAM and FLITF clock can be disabled only during sleep mode.
Parameters:
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None
Note:
After reset, the peripheral clock (used for registers read/write access) is disabled and the application software has to enable this clock before using it.
Parameters:
RCC_AHBPeriph,:specifies the AHB peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_AHBPeriph_GPIOA
  • RCC_AHBPeriph_GPIOB
  • RCC_AHBPeriph_GPIOC
  • RCC_AHBPeriph_GPIOD
  • RCC_AHBPeriph_GPIOE
  • RCC_AHBPeriph_GPIOH
  • RCC_AHBPeriph_CRC
  • RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
  • RCC_AHBPeriph_DMA1
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_AHB_PERIPH, and RCC.

void RCC_AHBPeriphResetCmd ( uint32_t  RCC_AHBPeriph,
FunctionalState  NewState 
)

Forces or releases AHB peripheral reset.

Parameters:
RCC_AHBPeriph,:specifies the AHB peripheral to reset. This parameter can be any combination of the following values:
  • RCC_AHBPeriph_GPIOA
  • RCC_AHBPeriph_GPIOB
  • RCC_AHBPeriph_GPIOC
  • RCC_AHBPeriph_GPIOD
  • RCC_AHBPeriph_GPIOE
  • RCC_AHBPeriph_GPIOH
  • RCC_AHBPeriph_CRC
  • RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
  • RCC_AHBPeriph_DMA1
NewState,:new state of the specified peripheral reset. This parameter can be: ENABLE or DISABLE.
Return values:
None

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_AHB_PERIPH, and RCC.

void RCC_AHBPeriphClockLPModeCmd ( uint32_t  RCC_AHBPeriph,
FunctionalState  NewState 
)

Enables or disables the AHB peripheral clock during SLEEP mode.

Note:
- Peripheral clock gating in SLEEP mode can be used to further reduce power consumption.
  • After wakeup from SLEEP mode, the peripheral clock is enabled again.
  • By default, all peripheral clocks are enabled during SLEEP mode.
Parameters:
RCC_AHBPeriph,:specifies the AHB peripheral to gates its clock. This parameter can be any combination of the following values:
  • RCC_AHBPeriph_GPIOA
  • RCC_AHBPeriph_GPIOB
  • RCC_AHBPeriph_GPIOC
  • RCC_AHBPeriph_GPIOD
  • RCC_AHBPeriph_GPIOE
  • RCC_AHBPeriph_GPIOH
  • RCC_AHBPeriph_CRC
  • RCC_AHBPeriph_FLITF (has effect only when the Flash memory is in power down mode)
  • RCC_AHBPeriph_SRAM
  • RCC_AHBPeriph_DMA1
NewState,:new state of the specified peripheral clock. This parameter can be: ENABLE or DISABLE.
Return values:
None

References assert_param, DISABLE, IS_FUNCTIONAL_STATE, IS_RCC_AHB_LPMODE_PERIPH, and RCC.