#include <cfg/os.h>
#include <stdint.h>
#include <string.h>
#include <sys/heap.h>
#include <sys/timer.h>
#include <dev/phy.h>
#include <stdio.h>
Data Structures | |
struct | phy_bit_descr_t |
struct | phy_status_descr_t |
Defines | |
#define | PHPRINTF(args,...) printf(args,##__VA_ARGS__); fflush(stdout); |
#define | PHY_BMCR 0x00 |
#define | PHY_BMSR 0x01 |
#define | PHY_ID1 0x02 |
#define | PHY_ID2 0x03 |
#define | PHY_ANAR 0x04 |
#define | PHY_ANLP 0x05 |
#define | PHY_ANER 0x06 |
#define | PHY_ANTR 0x07 |
#define | PHY_BMCR_RES 0x8000 |
#define | PHY_BMCR_LOOP 0x4000 |
#define | PHY_BMCR_SPEED 0x2000 |
#define | PHY_BMCR_ANEG 0x1000 |
#define | PHY_BMCR_PDWN 0x0800 |
#define | PHY_BMCR_ISO 0x0400 |
#define | PHY_BMCR_ANST 0x0200 |
#define | PHY_BMCR_DUPX 0x0100 |
#define | PHYSET_COLTEST 0x0080 |
#define | PHY_BMSR_CT4 0x8000 |
#define | PHY_BMSR_C100FD 0x4000 |
#define | PHY_BMSR_C100HD 0x2000 |
#define | PHY_BMSR_C10FD 0x1000 |
#define | PHY_BMSR_C10HD 0x0800 |
#define | PHY_BMSR_CPRE 0x0040 |
#define | PHY_BMSR_CANEG 0x0008 |
#define | PHY_BMSR_CEXT 0x0001 |
#define | PHY_BMSR_CMSK 0xF849 |
#define | PHY_BMSR_ANEG 0x0020 |
#define | PHY_BMSR_RFLT 0x0010 |
#define | PHY_BMSR_LNK 0x0004 |
#define | PHY_BMSR_JAB 0x0002 |
#define | PHY_BMSR_SMSK 0x0036 |
#define | phyw(reg, val) phydcb->mdiow( reg, val) |
#define | phyr(reg) phydcb->mdior( reg) |
#define | NutPhyGetStatus(void) phyr( PHY_BMSR)) |
Read PHY's Basic Mode Status Register. | |
Enumerations | |
enum | { PHY_BIT_DESCR_10M = 0, PHY_BIT_DESCR_100M, PHY_BIT_DESCR_1000M, PHY_BIT_DESCR_DUPLX, PHY_BIT_DESCR_POE, PHY_BIT_DESCR_MAX } |
Functions | |
int | NutPhyCtl (uint16_t ctl, uint32_t *par) |
Control PHY Options. | |
int | NutRegisterPhy (uint8_t mda, void(*mdiow)(uint8_t, uint16_t), uint16_t(*mdior)(uint8_t)) |
Register and initialize PHY communication. | |
Variables | |
PHYDCB * | phydcb = NULL |
enum { ... } | phy_bit_descr_nr |
phy_status_descr_t | phy_status_descr [] |
#define PHPRINTF | ( | args, | |
... | |||
) | printf(args,##__VA_ARGS__); fflush(stdout); |
Referenced by NutPhyCtl(), and NutRegisterPhy().
#define PHY_BMCR 0x00 |
Referenced by NutPhyCtl().
#define PHY_BMSR 0x01 |
Referenced by NutPhyCtl().
#define PHY_ID1 0x02 |
Referenced by NutRegisterPhy().
#define PHY_ID2 0x03 |
Referenced by NutRegisterPhy().
#define PHY_ANAR 0x04 |
#define PHY_ANLP 0x05 |
#define PHY_ANER 0x06 |
#define PHY_ANTR 0x07 |
#define PHY_BMCR_RES 0x8000 |
Referenced by NutPhyCtl().
#define PHY_BMCR_LOOP 0x4000 |
Referenced by NutPhyCtl().
#define PHY_BMCR_SPEED 0x2000 |
Referenced by NutPhyCtl().
#define PHY_BMCR_ANEG 0x1000 |
Referenced by NutPhyCtl().
#define PHY_BMCR_PDWN 0x0800 |
Referenced by NutPhyCtl().
#define PHY_BMCR_ISO 0x0400 |
Referenced by NutPhyCtl().
#define PHY_BMCR_ANST 0x0200 |
Referenced by NutPhyCtl().
#define PHY_BMCR_DUPX 0x0100 |
Referenced by NutPhyCtl().
#define PHYSET_COLTEST 0x0080 |
#define PHY_BMSR_CT4 0x8000 |
#define PHY_BMSR_C100FD 0x4000 |
#define PHY_BMSR_C100HD 0x2000 |
#define PHY_BMSR_C10FD 0x1000 |
#define PHY_BMSR_C10HD 0x0800 |
#define PHY_BMSR_CPRE 0x0040 |
#define PHY_BMSR_CANEG 0x0008 |
#define PHY_BMSR_CEXT 0x0001 |
#define PHY_BMSR_CMSK 0xF849 |
#define PHY_BMSR_ANEG 0x0020 |
Referenced by NutPhyCtl().
#define PHY_BMSR_RFLT 0x0010 |
#define PHY_BMSR_LNK 0x0004 |
Referenced by NutPhyCtl().
#define PHY_BMSR_JAB 0x0002 |
#define PHY_BMSR_SMSK 0x0036 |
#define phyw | ( | reg, | |
val | |||
) | phydcb->mdiow( reg, val) |
Referenced by NutPhyCtl().
#define phyr | ( | reg | ) | phydcb->mdior( reg) |
Referenced by NutPhyCtl(), and NutRegisterPhy().
#define NutPhyGetStatus | ( | void | ) | phyr( PHY_BMSR)) |
Read PHY's Basic Mode Status Register.
None. |
anonymous enum |
Control PHY Options.
This function controls the physical layer chip. Give
ctl | is the PHY option to control or test. |
par | Pointer to value of 1 to set, 0 to reset an option or the return of a value test. |
References NutDelay(), _PHYDCB::oui, PHPRINTF, PHY_BIT_DESCR_1000M, PHY_BIT_DESCR_100M, PHY_BIT_DESCR_10M, PHY_BIT_DESCR_DUPLX, PHY_BIT_DESCR_POE, PHY_BMCR, PHY_BMCR_ANEG, PHY_BMCR_ANST, PHY_BMCR_DUPX, PHY_BMCR_ISO, PHY_BMCR_LOOP, PHY_BMCR_PDWN, PHY_BMCR_RES, PHY_BMCR_SPEED, PHY_BMSR, PHY_BMSR_ANEG, PHY_BMSR_LNK, PHY_CTL_AUTONEG, PHY_CTL_AUTONEG_RE, PHY_CTL_DUPLEX, PHY_CTL_ISOLATE, PHY_CTL_LOOPBACK, PHY_CTL_POWERDOWN, PHY_CTL_RESET, PHY_CTL_SPEED, PHY_GET_LINK, PHY_GET_POE, PHY_GET_REGVAL, PHY_GET_STATUS, PHY_SET_REGVAL, PHY_STATUS_1000M, PHY_STATUS_100M, PHY_STATUS_10M, PHY_STATUS_AUTONEG_OK, PHY_STATUS_CON_UNKNOWN, phy_status_descr, PHY_STATUS_FULLDUPLEX, PHY_STATUS_HAS_LINK, phyr, phyw, and rc.
Register and initialize PHY communication.
This function registers a PHY for use by an EMAC. For communication tests, the function reads out the OUI and Model/Revision registers of the PHY.
mda | id the PHY's address on the MDIO interface bus of the EMAC. |
mdiow | Function provided by EMAC driver to write PHY regisers. |
mdior | Function provided by EMAC driver to read PHY regisers. |
References _PHYDCB::addr, _PHYDCB::mdior, _PHYDCB::mdiow, NULL, NutHeapAlloc, _PHYDCB::oui, PHPRINTF, PHY_ID1, PHY_ID2, phyr, and rc.
Referenced by DmInit().
enum { ... } phy_bit_descr_nr |
{ { DM9000, { {17, 0x3000}, {17, 0xC000}, {0, 0}, {17, 0xA000}, {0, 0} } }, { DM9000A, { {17, 0x3000}, {17, 0xC000}, {0, 0}, {17, 0xA000}, {0, 0} } }, { DM9000B, { {17, 0x3000}, {17, 0xC000}, {0, 0}, {17, 0xA000}, {0, 0} } }, { DM9161, { {17, 0x3000}, {17, 0xC000}, {0, 0}, {17, 0xA000}, {0, 0} } }, { LAN8700, { {31, 0x0004}, {31, 0x0008}, {0, 0}, {31, 0x0010}, {0, 0} } }, { LAN8700r4, { {31, 0x0004}, {31, 0x0008}, {0, 0}, {31, 0x0010}, {0, 0} } }, { LAN8710, { {31, 0x0004}, {31, 0x0008}, {0, 0}, {31, 0x0010}, {0, 0} } }, { LAN8720A, { {31, 0x0004}, {31, 0x0008}, {0, 0}, {31, 0x0010}, {0, 0} } }, { KS8721, { {31, 0x0004}, {31, 0x0008}, {0, 0}, {31, 0x0010}, {0, 0} } }, }
Referenced by NutPhyCtl().