#include <cfg/phycfg.h>
Go to the source code of this file.
Data Structures | |
struct | _PHYDCB |
Defines | |
#define | PHY_AUTO 0x00000000 |
#define | PHY_ANY 0xFFFFFFFF |
#define | AM79C875 0x00225540 |
#define | DM9161 0x0181B880 |
#define | DM9161A 0x0181B8A0 |
#define | DM9161B 0x0181B8B0 |
#define | DM9000 0x0181B8C0 |
#define | DM9000A 0x0181B8A0 |
#define | DM9000B 0x0181B8B0 |
#define | DP83838 0x20005C90 |
#define | DP83848 0x20005CA0 |
#define | KS8721 0x00221610 |
#define | KS8851 0x00008870 |
#define | STE100P 0x1C040010 |
#define | LAN8700 0x0007C0C0 |
#define | LAN8700r4 0x0007C0C4 |
#define | LAN8710 0x0007C0F0 |
#define | LAN8720 0x0007C0F0 |
#define | LAN8720A 0x0007C0F1 |
#define | OUIMSK_VEN 0x3FFFC000 |
#define | OUIMSK_DEV 0x00003FF0 |
#define | OUIMSK_REV 0x0000000F |
#define | PHY_STATUS_HAS_LINK 0x00000001 |
#define | PHY_STATUS_10M 0x00000002 |
#define | PHY_STATUS_100M 0x00000004 |
#define | PHY_STATUS_1000M 0x00000008 |
#define | PHY_STATUS_FULLDUPLEX 0x00000010 |
#define | PHY_STATUS_AUTONEG_OK 0x00000020 |
#define | PHY_STATUS_CON_UNKNOWN 0x00000040 |
#define | PHY_CTL_RESET 0x0001 |
#define | PHY_CTL_LOOPBACK 0x0002 |
#define | PHY_CTL_SPEED 0x0003 |
#define | PHY_CTL_AUTONEG 0x0004 |
#define | PHY_CTL_POWERDOWN 0x0005 |
#define | PHY_CTL_ISOLATE 0x0006 |
#define | PHY_CTL_DUPLEX 0x0007 |
#define | PHY_CTL_AUTONEG_RE 0x0008 |
#define | PHY_GET_LINK 0x0100 |
#define | PHY_GET_STATUS 0x0101 |
#define | PHY_GET_POE 0x0102 |
#define | PHY_GET_REGVAL 0x0103 |
#define | PHY_SET_REGVAL 0x0104 |
Typedefs | |
typedef struct _PHYDCB | PHYDCB |
Functions | |
uint16_t | NutPhyGetStatus (void) |
int | NutPhyCtl (uint16_t ctl, uint32_t *par) |
Control PHY Options. | |
int | NutRegisterPhy (uint8_t mda, void(*mdiow)(uint8_t, uint16_t), uint16_t(*mdior)(uint8_t)) |
Register and initialize PHY communication. |
#define PHY_AUTO 0x00000000 |
#define PHY_ANY 0xFFFFFFFF |
#define AM79C875 0x00225540 |
#define DM9161 0x0181B880 |
#define DM9161A 0x0181B8A0 |
#define DM9161B 0x0181B8B0 |
#define DM9000 0x0181B8C0 |
#define DM9000A 0x0181B8A0 |
#define DM9000B 0x0181B8B0 |
#define DP83838 0x20005C90 |
#define DP83848 0x20005CA0 |
#define KS8721 0x00221610 |
#define KS8851 0x00008870 |
#define STE100P 0x1C040010 |
#define LAN8700 0x0007C0C0 |
#define LAN8700r4 0x0007C0C4 |
#define LAN8710 0x0007C0F0 |
#define LAN8720 0x0007C0F0 |
#define LAN8720A 0x0007C0F1 |
#define OUIMSK_VEN 0x3FFFC000 |
#define OUIMSK_DEV 0x00003FF0 |
#define OUIMSK_REV 0x0000000F |
#define PHY_STATUS_HAS_LINK 0x00000001 |
Referenced by NutPhyCtl().
#define PHY_STATUS_10M 0x00000002 |
Referenced by NutPhyCtl().
#define PHY_STATUS_100M 0x00000004 |
Referenced by NutPhyCtl().
#define PHY_STATUS_1000M 0x00000008 |
Referenced by NutPhyCtl().
#define PHY_STATUS_FULLDUPLEX 0x00000010 |
Referenced by NutPhyCtl().
#define PHY_STATUS_AUTONEG_OK 0x00000020 |
Referenced by NutPhyCtl().
#define PHY_STATUS_CON_UNKNOWN 0x00000040 |
Referenced by NutPhyCtl().
#define PHY_CTL_RESET 0x0001 |
Referenced by NutPhyCtl().
#define PHY_CTL_LOOPBACK 0x0002 |
Referenced by NutPhyCtl().
#define PHY_CTL_SPEED 0x0003 |
Referenced by NutPhyCtl().
#define PHY_CTL_AUTONEG 0x0004 |
Referenced by NutPhyCtl().
#define PHY_CTL_POWERDOWN 0x0005 |
Referenced by NutPhyCtl().
#define PHY_CTL_ISOLATE 0x0006 |
Referenced by NutPhyCtl().
#define PHY_CTL_DUPLEX 0x0007 |
Referenced by NutPhyCtl().
#define PHY_CTL_AUTONEG_RE 0x0008 |
Referenced by NutPhyCtl().
#define PHY_GET_LINK 0x0100 |
Referenced by NutPhyCtl().
#define PHY_GET_STATUS 0x0101 |
Referenced by NutPhyCtl().
#define PHY_GET_POE 0x0102 |
Referenced by NutPhyCtl().
#define PHY_GET_REGVAL 0x0103 |
Referenced by NutPhyCtl().
#define PHY_SET_REGVAL 0x0104 |
Referenced by NutPhyCtl().
uint16_t NutPhyGetStatus | ( | void | ) |
Control PHY Options.
This function controls the physical layer chip. Give
ctl | is the PHY option to control or test. |
par | Pointer to value of 1 to set, 0 to reset an option or the return of a value test. |
References NutDelay(), _PHYDCB::oui, PHPRINTF, PHY_BIT_DESCR_1000M, PHY_BIT_DESCR_100M, PHY_BIT_DESCR_10M, PHY_BIT_DESCR_DUPLX, PHY_BIT_DESCR_POE, PHY_BMCR, PHY_BMCR_ANEG, PHY_BMCR_ANST, PHY_BMCR_DUPX, PHY_BMCR_ISO, PHY_BMCR_LOOP, PHY_BMCR_PDWN, PHY_BMCR_RES, PHY_BMCR_SPEED, PHY_BMSR, PHY_BMSR_ANEG, PHY_BMSR_LNK, PHY_CTL_AUTONEG, PHY_CTL_AUTONEG_RE, PHY_CTL_DUPLEX, PHY_CTL_ISOLATE, PHY_CTL_LOOPBACK, PHY_CTL_POWERDOWN, PHY_CTL_RESET, PHY_CTL_SPEED, PHY_GET_LINK, PHY_GET_POE, PHY_GET_REGVAL, PHY_GET_STATUS, PHY_SET_REGVAL, PHY_STATUS_1000M, PHY_STATUS_100M, PHY_STATUS_10M, PHY_STATUS_AUTONEG_OK, PHY_STATUS_CON_UNKNOWN, phy_status_descr, PHY_STATUS_FULLDUPLEX, PHY_STATUS_HAS_LINK, phyr, phyw, and rc.
Register and initialize PHY communication.
This function registers a PHY for use by an EMAC. For communication tests, the function reads out the OUI and Model/Revision registers of the PHY.
mda | id the PHY's address on the MDIO interface bus of the EMAC. |
mdiow | Function provided by EMAC driver to write PHY regisers. |
mdior | Function provided by EMAC driver to read PHY regisers. |
References _PHYDCB::addr, _PHYDCB::mdior, _PHYDCB::mdiow, NULL, NutHeapAlloc, _PHYDCB::oui, PHPRINTF, PHY_ID1, PHY_ID2, phyr, and rc.
Referenced by DmInit().