Defines |
#define | MC_RCR_OFF 0x00000000 |
| MC remap control register offset.
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#define | MC_RCR (MC_BASE + MC_RCR_OFF) |
| MC remap control register address.
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#define | MC_RCB 0x00000001 |
| Remap command.
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#define | MC_ASR_OFF 0x00000004 |
| MC abort status register offset.
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#define | MC_ASR (MC_BASE + MC_ASR_OFF) |
| MC abort status register address.
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#define | MC_UNDADD 0x00000001 |
| Undefined Addess Abort status.
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#define | MC_MISADD 0x00000002 |
| Misaligned Addess Abort status.
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#define | MC_ABTSZ_MASK 0x00000300 |
| Abort size status mask.
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#define | MC_ABTSZ_BYTE 0x00000000 |
| Byte size abort.
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#define | MC_ABTSZ_HWORD 0x00000100 |
| Half-word size abort.
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#define | MC_ABTSZ_WORD 0x00000200 |
| Word size abort.
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#define | MC_ABTTYP_MASK 0x00000C00 |
| Abort type status mask.
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#define | MC_ABTTYP_DATAR 0x00000000 |
| Data read abort.
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#define | MC_ABTTYP_DATAW 0x00000400 |
| Data write abort.
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#define | MC_ABTTYP_FETCH 0x00000800 |
| Code fetch abort.
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#define | MC_MST_EMAC 0x00010000 |
| EMAC abort source.
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#define | MC_MST_PDC 0x00020000 |
| PDC abort source.
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#define | MC_MST_ARM 0x00040000 |
| ARM abort source.
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#define | MC_SVMST_EMAC 0x01000000 |
| Saved EMAC abort source.
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#define | MC_SVMST_PDC 0x02000000 |
| Saved PDC abort source.
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#define | MC_SVMST_ARM 0x04000000 |
| Saved ARM abort source.
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#define | MC_AASR_OFF 0x00000008 |
| MC abort address status register offset.
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#define | MC_AASR (MC_BASE + MC_AASR_OFF) |
| MC abort address status register address.
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#define | MC_FMR_EFC0_OFF 0x00000060 |
| MC flash mode register bank 0 offset.
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#define | MC_FMR_EFC0 (MC_BASE + MC_FMR_EFC0_OFF) |
| MC flash mode register bank 0 address.
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#define | MC_FMR_EFC1_OFF 0x00000070 |
| MC flash mode register bank 1 offset.
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#define | MC_FMR_EFC1 (MC_BASE + MC_FMR_EFC1_OFF) |
| MC flash mode register bank 1 address.
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#define | MC_FMR_OFF MC_FMR_EFC0_OFF |
| MC flash mode register offset.
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#define | MC_FMR MC_FMR_EFC0 |
| MC flash mode register address.
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#define | MC_FRDY 0x00000001 |
| Flash ready.
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#define | MC_LOCKE 0x00000004 |
| Lock error.
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#define | MC_PROGE 0x00000008 |
| Programming error.
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#define | MC_NEBP 0x00000080 |
| No erase before programming.
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#define | MC_FWS_LSB 8 |
| Flash wait state LSB.
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#define | MC_FWS_MASK 0x00000300 |
| Flash wait state mask.
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#define | MC_FWS_1R2W 0x00000000 |
| 1 cycle for read, 2 for write operations.
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#define | MC_FWS_2R3W 0x00000100 |
| 2 cycles for read, 3 for write operations.
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#define | MC_FWS_3R4W 0x00000200 |
| 3 cycles for read, 4 for write operations.
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#define | MC_FWS_4R4W 0x00000300 |
| 4 cycles for read and write operations.
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#define | MC_FMCN_LSB 16 |
| Flash microsecond cycle number LSB.
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#define | MC_FMCN_MASK 0x00FF0000 |
| Flash microsecond cycle number mask.
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#define | MC_FCR_EFC0_OFF 0x00000064 |
| MC flash mode register bank 0 offset.
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#define | MC_FCR_EFC0 (MC_BASE + MC_FCR_EFC0_OFF) |
| MC flash mode register bank 0 address.
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#define | MC_FCR_EFC1_OFF 0x00000074 |
| MC flash mode register bank 1 offset.
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#define | MC_FCR_EFC1 (MC_BASE + MC_FCR_EFC1_OFF) |
| MC flash mode register bank 1 address.
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#define | MC_FCR_OFF MC_FCR_EFC0_OFF |
| MC flash command register offset.
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#define | MC_FCR MC_FCR_EFC0 |
| MC flash command register address.
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#define | MC_FCMD_MASK 0x0000000F |
| Flash command mask.
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#define | MC_FCMD_NOP 0x00000000 |
| No command.
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#define | MC_FCMD_WP 0x00000001 |
| Write page.
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#define | MC_FCMD_SLB 0x00000002 |
| Set lock bit.
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#define | MC_FCMD_WPL 0x00000003 |
| Write page and lock.
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#define | MC_FCMD_CLB 0x00000004 |
| Clear lock bit.
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#define | MC_FCMD_EA 0x00000008 |
| Erase all.
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#define | MC_FCMD_SGPB 0x0000000B |
| Set general purpose NVM bit.
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#define | MC_FCMD_CGPB 0x0000000D |
| Clear general purpose NVM bit.
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#define | MC_FCMD_SSB 0x0000000F |
| Set security bit.
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#define | MC_PAGEN_MASK 0x0003FF00 |
| Page number mask.
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#define | MC_KEY 0x5A000000 |
| Writing protect key.
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#define | MC_FSR_EFC0_OFF 0x00000068 |
| MC flash mode register bank 0 offset.
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#define | MC_FSR_EFC0 (MC_BASE + MC_FSR_EFC0_OFF) |
| MC flash mode register bank 0 address.
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#define | MC_FSR_EFC1_OFF 0x00000078 |
| MC flash mode register bank 1 offset.
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#define | MC_FSR_EFC1 (MC_BASE + MC_FSR_EFC1_OFF) |
| MC flash mode register bank 1 address.
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#define | MC_FSR_OFF MC_FSR_EFC0_OFF |
| MC flash status register offset.
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#define | MC_FSR MC_FSR_EFC0 |
| MC flash status register address.
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#define | MC_SECURITY 0x00000010 |
| Security bit status.
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#define | MC_GPNVM0 0x00000100 |
| General purpose NVM bit 0.
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#define | MC_GPNVM1 0x00000200 |
| General purpose NVM bit 1.
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#define | MC_GPNVM2 0x00000400 |
| General purpose NVM bit 2.
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#define | MC_LOCKS0 0x00010000 |
| Lock region 0 lock status.
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#define | MC_LOCKS1 0x00020000 |
| Lock region 1 lock status.
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#define | MC_LOCKS2 0x00040000 |
| Lock region 2 lock status.
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#define | MC_LOCKS3 0x00080000 |
| Lock region 3 lock status.
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#define | MC_LOCKS4 0x00100000 |
| Lock region 4 lock status.
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#define | MC_LOCKS5 0x00200000 |
| Lock region 5 lock status.
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#define | MC_LOCKS6 0x00400000 |
| Lock region 6 lock status.
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#define | MC_LOCKS7 0x00800000 |
| Lock region 7 lock status.
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#define | MC_LOCKS8 0x01000000 |
| Lock region 8 lock status.
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#define | MC_LOCKS9 0x02000000 |
| Lock region 9 lock status.
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#define | MC_LOCKS10 0x04000000 |
| Lock region 10 lock status.
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#define | MC_LOCKS11 0x08000000 |
| Lock region 11 lock status.
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#define | MC_LOCKS12 0x10000000 |
| Lock region 12 lock status.
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#define | MC_LOCKS13 0x20000000 |
| Lock region 13 lock status.
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#define | MC_LOCKS14 0x40000000 |
| Lock region 14 lock status.
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#define | MC_LOCKS15 0x80000000 |
| Lock region 15 lock status.
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