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00047 #include <arch/arm.h>
00048 #include <dev/irqreg.h>
00049
00050 #if defined(ADC_ID)
00051
00052 #ifndef NUT_IRQPRI_ADC
00053 #define NUT_IRQPRI_ADC 4
00054 #endif
00055
00056 static int AdcIrqCtl(int cmd, void *param);
00057
00058 IRQ_HANDLER sig_ADC = {
00059 #ifdef NUT_PERFMON
00060 0,
00061 #endif
00062 NULL,
00063 NULL,
00064 AdcIrqCtl
00065 };
00066
00070 static void AdcIrqEntry(void) __attribute__ ((naked));
00071 void AdcIrqEntry(void)
00072 {
00073 IRQ_ENTRY();
00074 #ifdef NUT_PERFMON
00075 sig_ADC.ir_count++;
00076 #endif
00077 if (sig_ADC.ir_handler) {
00078 (sig_ADC.ir_handler) (sig_ADC.ir_arg);
00079 }
00080 IRQ_EXIT();
00081 }
00082
00100 static int AdcIrqCtl(int cmd, void *param)
00101 {
00102 int rc = 0;
00103 unsigned int *ival = (unsigned int *)param;
00104 int_fast8_t enabled = inr(AIC_IMR) & _BV(ADC_ID);
00105
00106
00107 if (enabled) {
00108 outr(AIC_IDCR, _BV(ADC_ID));
00109 }
00110
00111 switch(cmd) {
00112 case NUT_IRQCTL_INIT:
00113
00114 outr(AIC_SVR(ADC_ID), (unsigned int)AdcIrqEntry);
00115
00116 outr(AIC_SMR(ADC_ID), AIC_SRCTYPE_INT_EDGE_TRIGGERED | NUT_IRQPRI_ADC);
00117
00118 outr(AIC_ICCR, _BV(ADC_ID));
00119 break;
00120 case NUT_IRQCTL_STATUS:
00121 if (enabled) {
00122 *ival |= 1;
00123 }
00124 else {
00125 *ival &= ~1;
00126 }
00127 break;
00128 case NUT_IRQCTL_ENABLE:
00129 enabled = 1;
00130 break;
00131 case NUT_IRQCTL_DISABLE:
00132 enabled = 0;
00133 break;
00134 case NUT_IRQCTL_GETMODE:
00135 {
00136 unsigned int val = inr(AIC_SMR(ADC_ID)) & AIC_SRCTYPE;
00137 if (val == AIC_SRCTYPE_INT_LEVEL_SENSITIVE || val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00138 *ival = NUT_IRQMODE_LEVEL;
00139 } else {
00140 *ival = NUT_IRQMODE_EDGE;
00141 }
00142 }
00143 break;
00144 case NUT_IRQCTL_SETMODE:
00145 if (*ival == NUT_IRQMODE_LEVEL) {
00146 outr(AIC_SMR(ADC_ID), (inr(AIC_SMR(ADC_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE);
00147 } else if (*ival == NUT_IRQMODE_EDGE) {
00148 outr(AIC_SMR(ADC_ID), (inr(AIC_SMR(ADC_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_EDGE_TRIGGERED);
00149 } else {
00150 rc = -1;
00151 }
00152 break;
00153 case NUT_IRQCTL_GETPRIO:
00154 *ival = inr(AIC_SMR(ADC_ID)) & AIC_PRIOR;
00155 break;
00156 case NUT_IRQCTL_SETPRIO:
00157 outr(AIC_SMR(ADC_ID), (inr(AIC_SMR(ADC_ID)) & ~AIC_PRIOR) | *ival);
00158 break;
00159 #ifdef NUT_PERFMON
00160 case NUT_IRQCTL_GETCOUNT:
00161 *ival = (unsigned int)sig_ADC.ir_count;
00162 sig_ADC.ir_count = 0;
00163 break;
00164 #endif
00165 default:
00166 rc = -1;
00167 break;
00168 }
00169
00170
00171 if (enabled) {
00172 outr(AIC_IECR, _BV(ADC_ID));
00173 }
00174 return rc;
00175 }
00176
00177 #endif