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00058 #include <arch/arm.h>
00059 #include <dev/irqreg.h>
00060
00061 #ifndef NUT_IRQPRI_FIQ
00062 #define NUT_IRQPRI_FIQ 4
00063 #endif
00064
00065 static int FastIrqCtl(int cmd, void *param);
00066
00067 IRQ_HANDLER sig_FIQ = {
00068 #ifdef NUT_PERFMON
00069 0,
00070 #endif
00071 NULL,
00072 NULL,
00073 FastIrqCtl
00074 };
00075
00081 static void FastIrqEntry(void) __attribute__ ((naked));
00082 void FastIrqEntry(void)
00083 {
00084 FIQ_ENTRY();
00085 #ifdef NUT_PERFMON
00086 sig_FIQ.ir_count++;
00087 #endif
00088 if (sig_FIQ.ir_handler) {
00089 (sig_FIQ.ir_handler) (sig_FIQ.ir_arg);
00090 }
00091 FIQ_EXIT();
00092 }
00093
00109 static int FastIrqCtl(int cmd, void *param)
00110 {
00111 int rc = 0;
00112 unsigned int *ival = (unsigned int *)param;
00113 int_fast8_t enabled = inr(AIC_IMR) & _BV(FIQ_ID);
00114
00115
00116 if (enabled) {
00117 outr(AIC_IDCR, _BV(FIQ_ID));
00118 }
00119
00120 switch(cmd) {
00121 case NUT_IRQCTL_INIT:
00122
00123 outr(AIC_SVR(FIQ_ID), (unsigned int)FastIrqEntry);
00124
00125 outr(AIC_SMR(FIQ_ID), AIC_SRCTYPE_EXT_NEGATIVE_EDGE | NUT_IRQPRI_FIQ);
00126
00127 outr(AIC_ICCR, _BV(FIQ_ID));
00128 break;
00129 case NUT_IRQCTL_STATUS:
00130 if (enabled) {
00131 *ival |= 1;
00132 }
00133 else {
00134 *ival &= ~1;
00135 }
00136 break;
00137 case NUT_IRQCTL_ENABLE:
00138 enabled = 1;
00139 break;
00140 case NUT_IRQCTL_DISABLE:
00141 enabled = 0;
00142 break;
00143 case NUT_IRQCTL_GETMODE:
00144 {
00145 unsigned int val = inr(AIC_SMR(FIQ_ID)) & AIC_SRCTYPE;
00146 if (val == AIC_SRCTYPE_EXT_LOW_LEVEL) {
00147 *ival = NUT_IRQMODE_LOWLEVEL;
00148 } else if (val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00149 *ival = NUT_IRQMODE_HIGHLEVEL;
00150 } else if (val == AIC_SRCTYPE_EXT_POSITIVE_EDGE) {
00151 *ival = NUT_IRQMODE_RISINGEDGE;
00152 } else {
00153 *ival = NUT_IRQMODE_FALLINGEDGE;
00154 }
00155 }
00156 break;
00157 case NUT_IRQCTL_SETMODE:
00158 if (*ival == NUT_IRQMODE_LOWLEVEL) {
00159 outr(AIC_SMR(FIQ_ID), (inr(AIC_SMR(FIQ_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_LOW_LEVEL);
00160 } else if (*ival == NUT_IRQMODE_HIGHLEVEL) {
00161 outr(AIC_SMR(FIQ_ID), (inr(AIC_SMR(FIQ_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_HIGH_LEVEL);
00162 } else if (*ival == NUT_IRQMODE_FALLINGEDGE) {
00163 outr(AIC_SMR(FIQ_ID), (inr(AIC_SMR(FIQ_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_NEGATIVE_EDGE);
00164 } else if (*ival == NUT_IRQMODE_RISINGEDGE) {
00165 outr(AIC_SMR(FIQ_ID), (inr(AIC_SMR(FIQ_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_POSITIVE_EDGE);
00166 } else {
00167 rc = -1;
00168 }
00169 break;
00170 #ifdef NUT_PERFMON
00171 case NUT_IRQCTL_GETCOUNT:
00172 *ival = (unsigned int)sig_FIQ.ir_count;
00173 sig_FIQ.ir_count = 0;
00174 break;
00175 #endif
00176 default:
00177 rc = -1;
00178 break;
00179 }
00180
00181
00182 if (enabled) {
00183 outr(AIC_IECR, _BV(FIQ_ID));
00184 #if defined(PMC_PCER)
00185 outr(PMC_PCER, _BV(FIQ_ID));
00186 #endif
00187 }
00188 return rc;
00189 }