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00053 #include <arch/arm.h>
00054 #include <dev/irqreg.h>
00055
00056 #ifndef NUT_IRQPRI_IRQ1
00057 #define NUT_IRQPRI_IRQ1 4
00058 #endif
00059
00060 static int Interrupt1Ctl(int cmd, void *param);
00061
00062 IRQ_HANDLER sig_INTERRUPT1 = {
00063 #ifdef NUT_PERFMON
00064 0,
00065 #endif
00066 NULL,
00067 NULL,
00068 Interrupt1Ctl
00069 };
00070
00074 static void Interrupt1Entry(void) __attribute__ ((naked));
00075 void Interrupt1Entry(void)
00076 {
00077 IRQ_ENTRY();
00078 #ifdef NUT_PERFMON
00079 sig_INTERRUPT1.ir_count++;
00080 #endif
00081 if (sig_INTERRUPT1.ir_handler) {
00082 (sig_INTERRUPT1.ir_handler) (sig_INTERRUPT1.ir_arg);
00083 }
00084 IRQ_EXIT();
00085 }
00086
00102 static int Interrupt1Ctl(int cmd, void *param)
00103 {
00104 int rc = 0;
00105 unsigned int *ival = (unsigned int *)param;
00106 int_fast8_t enabled = inr(AIC_IMR) & _BV(IRQ1_ID);
00107
00108
00109 if (enabled) {
00110 outr(AIC_IDCR, _BV(IRQ1_ID));
00111 }
00112
00113 switch(cmd) {
00114 case NUT_IRQCTL_INIT:
00115
00116 outr(AIC_SVR(IRQ1_ID), (unsigned int)Interrupt1Entry);
00117
00118 outr(AIC_SMR(IRQ1_ID), AIC_SRCTYPE_EXT_HIGH_LEVEL | NUT_IRQPRI_IRQ1);
00119
00120 outr(AIC_ICCR, _BV(IRQ1_ID));
00121 break;
00122 case NUT_IRQCTL_STATUS:
00123 if (enabled) {
00124 *ival |= 1;
00125 }
00126 else {
00127 *ival &= ~1;
00128 }
00129 break;
00130 case NUT_IRQCTL_ENABLE:
00131 enabled = 1;
00132 break;
00133 case NUT_IRQCTL_DISABLE:
00134 enabled = 0;
00135 break;
00136 case NUT_IRQCTL_GETMODE:
00137 {
00138 unsigned int val = inr(AIC_SMR(IRQ1_ID)) & AIC_SRCTYPE;
00139 if (val == AIC_SRCTYPE_EXT_LOW_LEVEL) {
00140 *ival = NUT_IRQMODE_LOWLEVEL;
00141 } else if (val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00142 *ival = NUT_IRQMODE_HIGHLEVEL;
00143 } else if (val == AIC_SRCTYPE_EXT_POSITIVE_EDGE) {
00144 *ival = NUT_IRQMODE_RISINGEDGE;
00145 } else {
00146 *ival = NUT_IRQMODE_FALLINGEDGE;
00147 }
00148 }
00149 break;
00150 case NUT_IRQCTL_SETMODE:
00151 if (*ival == NUT_IRQMODE_LOWLEVEL) {
00152 outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_LOW_LEVEL);
00153 } else if (*ival == NUT_IRQMODE_HIGHLEVEL) {
00154 outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_HIGH_LEVEL);
00155 } else if (*ival == NUT_IRQMODE_FALLINGEDGE) {
00156 outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_NEGATIVE_EDGE);
00157 } else if (*ival == NUT_IRQMODE_RISINGEDGE) {
00158 outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_EXT_POSITIVE_EDGE);
00159 } else {
00160 rc = -1;
00161 }
00162 break;
00163 case NUT_IRQCTL_GETPRIO:
00164 *ival = inr(AIC_SMR(IRQ1_ID)) & AIC_PRIOR;
00165 break;
00166 case NUT_IRQCTL_SETPRIO:
00167 outr(AIC_SMR(IRQ1_ID), (inr(AIC_SMR(IRQ1_ID)) & ~AIC_PRIOR) | *ival);
00168 break;
00169 #ifdef NUT_PERFMON
00170 case NUT_IRQCTL_GETCOUNT:
00171 *ival = (unsigned int)sig_INTERRUPT1.ir_count;
00172 sig_INTERRUPT1.ir_count = 0;
00173 break;
00174 #endif
00175 default:
00176 rc = -1;
00177 break;
00178 }
00179
00180
00181 if (enabled) {
00182 outr(AIC_IECR, _BV(IRQ1_ID));
00183 #if defined(PMC_PCER)
00184 outr(PMC_PCER, _BV(IRQ1_ID));
00185 #endif
00186 }
00187 return rc;
00188 }
00189