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00058 #include <arch/arm.h>
00059 #include <dev/irqreg.h>
00060
00061 #ifndef NUT_IRQPRI_PWMC
00062 #define NUT_IRQPRI_PWMC 5
00063 #endif
00064
00065 static int PulseWidthModulatorIrqCtl(int cmd, void *param);
00066
00067 IRQ_HANDLER sig_PWMC = {
00068 #ifdef NUT_PERFMON
00069 0,
00070 #endif
00071 NULL,
00072 NULL,
00073 PulseWidthModulatorIrqCtl
00074 };
00075
00079 static unsigned int dummy;
00080 static void PulseWidthModulatorIrqEntry(void) __attribute__ ((naked));
00081 void PulseWidthModulatorIrqEntry(void)
00082 {
00083 IRQ_ENTRY();
00084 #ifdef NUT_PERFMON
00085 sig_PWMC.ir_count++;
00086 #endif
00087 dummy = inr(PWMC_ISR);
00088 if (sig_PWMC.ir_handler) {
00089 (sig_PWMC.ir_handler) (sig_PWMC.ir_arg);
00090 }
00091 IRQ_EXIT();
00092 }
00093
00111 static int PulseWidthModulatorIrqCtl(int cmd, void *param)
00112 {
00113 int rc = 0;
00114 unsigned int *ival = (unsigned int *)param;
00115 int_fast8_t enabled = inr(AIC_IMR) & _BV(PWMC_ID);
00116
00117
00118 if (enabled) {
00119 outr(AIC_IDCR, _BV(PWMC_ID));
00120 }
00121
00122 switch(cmd) {
00123 case NUT_IRQCTL_INIT:
00124
00125 outr(AIC_SVR(PWMC_ID), (unsigned int)PulseWidthModulatorIrqEntry);
00126
00127 outr(AIC_SMR(PWMC_ID), AIC_SRCTYPE_EXT_HIGH_LEVEL | NUT_IRQPRI_PWMC);
00128
00129 outr(AIC_ICCR, _BV(PWMC_ID));
00130 break;
00131 case NUT_IRQCTL_STATUS:
00132 if (enabled) {
00133 *ival |= 1;
00134 }
00135 else {
00136 *ival &= ~1;
00137 }
00138 break;
00139 case NUT_IRQCTL_ENABLE:
00140 enabled = 1;
00141 break;
00142 case NUT_IRQCTL_DISABLE:
00143 enabled = 0;
00144 break;
00145 case NUT_IRQCTL_GETMODE:
00146 {
00147 unsigned int val = inr(AIC_SMR(PWMC_ID)) & AIC_SRCTYPE;
00148 if (val == AIC_SRCTYPE_INT_LEVEL_SENSITIVE || val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00149 *ival = NUT_IRQMODE_LEVEL;
00150 } else {
00151 *ival = NUT_IRQMODE_EDGE;
00152 }
00153 }
00154 break;
00155 case NUT_IRQCTL_SETMODE:
00156 if (*ival == NUT_IRQMODE_LEVEL) {
00157 outr(AIC_SMR(PWMC_ID), (inr(AIC_SMR(PWMC_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE);
00158 } else if (*ival == NUT_IRQMODE_EDGE) {
00159 outr(AIC_SMR(PWMC_ID), (inr(AIC_SMR(PWMC_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_EDGE_TRIGGERED);
00160 } else {
00161 rc = -1;
00162 }
00163 break;
00164 case NUT_IRQCTL_GETPRIO:
00165 *ival = inr(AIC_SMR(PWMC_ID)) & AIC_PRIOR;
00166 break;
00167 case NUT_IRQCTL_SETPRIO:
00168 outr(AIC_SMR(PWMC_ID), (inr(AIC_SMR(PWMC_ID)) & ~AIC_PRIOR) | *ival);
00169 break;
00170 #ifdef NUT_PERFMON
00171 case NUT_IRQCTL_GETCOUNT:
00172 *ival = (unsigned int)sig_PWMC.ir_count;
00173 sig_PWMC.ir_count = 0;
00174 break;
00175 #endif
00176 default:
00177 rc = -1;
00178 break;
00179 }
00180
00181
00182 if (enabled) {
00183 outr(AIC_IECR, _BV(PWMC_ID));
00184 }
00185 return rc;
00186 }