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00050 #include <arch/arm.h>
00051 #include <dev/irqreg.h>
00052
00053 #ifndef NUT_IRQPRI_TC2
00054 #define NUT_IRQPRI_TC2 4
00055 #endif
00056
00057 static int TimerCounter2IrqCtl(int cmd, void *param);
00058
00059 IRQ_HANDLER sig_TC2 = {
00060 #ifdef NUT_PERFMON
00061 0,
00062 #endif
00063 NULL,
00064 NULL,
00065 TimerCounter2IrqCtl
00066 };
00067
00071 static unsigned int dummy;
00072 static void TimerCounter2IrqEntry(void) __attribute__ ((naked));
00073 void TimerCounter2IrqEntry(void)
00074 {
00075 IRQ_ENTRY();
00076 #ifdef NUT_PERFMON
00077 sig_TC2.ir_count++;
00078 #endif
00079 dummy = inr(TC2_SR);
00080 if (sig_TC2.ir_handler) {
00081 (sig_TC2.ir_handler) (sig_TC2.ir_arg);
00082 }
00083 IRQ_EXIT();
00084 }
00085
00103 static int TimerCounter2IrqCtl(int cmd, void *param)
00104 {
00105 int rc = 0;
00106 unsigned int *ival = (unsigned int *)param;
00107 int_fast8_t enabled = inr(AIC_IMR) & _BV(TC2_ID);
00108
00109
00110 if (enabled) {
00111 outr(AIC_IDCR, _BV(TC2_ID));
00112 }
00113
00114 switch(cmd) {
00115 case NUT_IRQCTL_INIT:
00116
00117 outr(AIC_SVR(TC2_ID), (unsigned int)TimerCounter2IrqEntry);
00118
00119 outr(AIC_SMR(TC2_ID), AIC_SRCTYPE_INT_EDGE_TRIGGERED | NUT_IRQPRI_TC2);
00120
00121 outr(AIC_ICCR, _BV(TC2_ID));
00122 break;
00123 case NUT_IRQCTL_STATUS:
00124 if (enabled) {
00125 *ival |= 1;
00126 }
00127 else {
00128 *ival &= ~1;
00129 }
00130 break;
00131 case NUT_IRQCTL_ENABLE:
00132 enabled = 1;
00133 break;
00134 case NUT_IRQCTL_DISABLE:
00135 enabled = 0;
00136 break;
00137 case NUT_IRQCTL_GETMODE:
00138 {
00139 unsigned int val = inr(AIC_SMR(TC2_ID)) & AIC_SRCTYPE;
00140 if (val == AIC_SRCTYPE_INT_LEVEL_SENSITIVE || val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00141 *ival = NUT_IRQMODE_LEVEL;
00142 } else {
00143 *ival = NUT_IRQMODE_EDGE;
00144 }
00145 }
00146 break;
00147 case NUT_IRQCTL_SETMODE:
00148 if (*ival == NUT_IRQMODE_LEVEL) {
00149 outr(AIC_SMR(TC2_ID), (inr(AIC_SMR(TC2_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE);
00150 } else if (*ival == NUT_IRQMODE_EDGE) {
00151 outr(AIC_SMR(TC2_ID), (inr(AIC_SMR(TC2_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_EDGE_TRIGGERED);
00152 } else {
00153 rc = -1;
00154 }
00155 break;
00156 case NUT_IRQCTL_GETPRIO:
00157 *ival = inr(AIC_SMR(TC2_ID)) & AIC_PRIOR;
00158 break;
00159 case NUT_IRQCTL_SETPRIO:
00160 outr(AIC_SMR(TC2_ID), (inr(AIC_SMR(TC2_ID)) & ~AIC_PRIOR) | *ival);
00161 break;
00162 #ifdef NUT_PERFMON
00163 case NUT_IRQCTL_GETCOUNT:
00164 *ival = (unsigned int)sig_TC2.ir_count;
00165 sig_TC2.ir_count = 0;
00166 break;
00167 #endif
00168 default:
00169 rc = -1;
00170 break;
00171 }
00172
00173
00174 if (enabled) {
00175 outr(AIC_IECR, _BV(TC2_ID));
00176 }
00177 return rc;
00178 }