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00051 #include <arch/arm.h>
00052 #include <dev/irqreg.h>
00053
00054 #ifndef NUT_IRQPRI_UART1
00055 #define NUT_IRQPRI_UART1 4
00056 #endif
00057
00058 static int Uart1IrqCtl(int cmd, void *param);
00059
00060 IRQ_HANDLER sig_UART1 = {
00061 #ifdef NUT_PERFMON
00062 0,
00063 #endif
00064 NULL,
00065 NULL,
00066 Uart1IrqCtl
00067 };
00068
00072 static void Uart1IrqEntry(void) __attribute__ ((naked));
00073 void Uart1IrqEntry(void)
00074 {
00075 IRQ_ENTRY();
00076 #ifdef NUT_PERFMON
00077 sig_UART1.ir_count++;
00078 #endif
00079 if (sig_UART1.ir_handler) {
00080 (sig_UART1.ir_handler) (sig_UART1.ir_arg);
00081 }
00082 IRQ_EXIT();
00083 }
00084
00102 static int Uart1IrqCtl(int cmd, void *param)
00103 {
00104 int rc = 0;
00105 unsigned int *ival = (unsigned int *)param;
00106 int_fast8_t enabled = inr(AIC_IMR) & _BV(US1_ID);
00107
00108
00109 if (enabled) {
00110 outr(AIC_IDCR, _BV(US1_ID));
00111 }
00112
00113 switch(cmd) {
00114 case NUT_IRQCTL_INIT:
00115
00116 outr(AIC_SVR(US1_ID), (unsigned int)Uart1IrqEntry);
00117
00118 outr(AIC_SMR(US1_ID), AIC_SRCTYPE_INT_LEVEL_SENSITIVE | NUT_IRQPRI_UART1);
00119
00120 outr(AIC_ICCR, _BV(US1_ID));
00121 break;
00122 case NUT_IRQCTL_STATUS:
00123 if (enabled) {
00124 *ival |= 1;
00125 }
00126 else {
00127 *ival &= ~1;
00128 }
00129 break;
00130 case NUT_IRQCTL_ENABLE:
00131 enabled = 1;
00132 break;
00133 case NUT_IRQCTL_DISABLE:
00134 enabled = 0;
00135 break;
00136 case NUT_IRQCTL_GETMODE:
00137 {
00138 unsigned int val = inr(AIC_SMR(US1_ID)) & AIC_SRCTYPE;
00139 if (val == AIC_SRCTYPE_INT_LEVEL_SENSITIVE || val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
00140 *ival = NUT_IRQMODE_LEVEL;
00141 } else {
00142 *ival = NUT_IRQMODE_EDGE;
00143 }
00144 }
00145 break;
00146 case NUT_IRQCTL_SETMODE:
00147 if (*ival == NUT_IRQMODE_LEVEL) {
00148 outr(AIC_SMR(US1_ID), (inr(AIC_SMR(US1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE);
00149 } else if (*ival == NUT_IRQMODE_EDGE) {
00150 outr(AIC_SMR(US1_ID), (inr(AIC_SMR(US1_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_EDGE_TRIGGERED);
00151 } else {
00152 rc = -1;
00153 }
00154 break;
00155 case NUT_IRQCTL_GETPRIO:
00156 *ival = inr(AIC_SMR(US1_ID)) & AIC_PRIOR;
00157 break;
00158 case NUT_IRQCTL_SETPRIO:
00159 outr(AIC_SMR(US1_ID), (inr(AIC_SMR(US1_ID)) & ~AIC_PRIOR) | *ival);
00160 break;
00161 #ifdef NUT_PERFMON
00162 case NUT_IRQCTL_GETCOUNT:
00163 *ival = (unsigned int)sig_UART1.ir_count;
00164 sig_UART1.ir_count = 0;
00165 break;
00166 #endif
00167 default:
00168 rc = -1;
00169 break;
00170 }
00171
00172
00173 if (enabled) {
00174 outr(AIC_IECR, _BV(US1_ID));
00175 }
00176 return rc;
00177 }