ih_tc0.c

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/*
* $Log: ih_tc0.c,v $
*
*/

#include <arch/avr32.h>
#include <dev/irqreg.h>

#ifndef NUT_IRQPRI_TC0
#define NUT_IRQPRI_TC0  0
#endif

#define CHANNEL 0

static int TimerCounter0IrqCtl(int cmd, void *param);

IRQ_HANDLER sig_TC0 = {
#ifdef NUT_PERFMON
    0,                          /* Interrupt counter, ir_count. */
#endif
    NULL,                       /* Passed argument, ir_arg. */
    NULL,                       /* Handler subroutine, ir_handler. */
    TimerCounter0IrqCtl         /* Interrupt control, ir_ctl. */
};

static int TimerCounter0IrqCtl(int cmd, void *param)
{
    int rc = 0;
    unsigned int *ival = (unsigned int *) param;
    int_fast8_t enabled = inr(AIC_IMR) & _BV(TC0_ID);

    /* Disable interrupt. */
    if (enabled) {
        AVR32_TC.channel[CHANNEL].sr;
    }

    switch (cmd) {
    case NUT_IRQCTL_INIT:
        // GENERATE SIGNALS: Waveform operating mode.
        AVR32_TC.channel[CHANNEL].cmr = AVR32_TC_NONE << AVR32_TC_BSWTRG_OFFSET |
            AVR32_TC_NONE << AVR32_TC_BEEVT_OFFSET |
            AVR32_TC_NONE << AVR32_TC_BCPC_OFFSET |
            AVR32_TC_NONE << AVR32_TC_BCPB_OFFSET |
            AVR32_TC_NONE << AVR32_TC_ASWTRG_OFFSET |
            AVR32_TC_NONE << AVR32_TC_AEEVT_OFFSET |
            AVR32_TC_NONE << AVR32_TC_ACPC_OFFSET |
            AVR32_TC_NONE << AVR32_TC_ACPA_OFFSET |
            1 << AVR32_TC_WAVE_OFFSET |
            AVR32_TC_WAVSEL_UP_AUTO << AVR32_TC_WAVSEL_OFFSET |
            0 << AVR32_TC_ENETRG_OFFSET |
            0 << AVR32_TC_EEVT_OFFSET |
            AVR32_TC_EEVTEDG_NO_EDGE << AVR32_TC_EEVTEDG_OFFSET |
            0 << AVR32_TC_CPCDIS_OFFSET |
            0 << AVR32_TC_CPCSTOP_OFFSET |
            0 << AVR32_TC_BURST_OFFSET | 0 << AVR32_TC_CLKI_OFFSET | AVR32_TC_TCCLKS_TIMER_CLOCK3 << AVR32_TC_TCCLKS_OFFSET;



        break;
    case NUT_IRQCTL_STATUS:
        if (enabled) {
            *ival |= 1;
        } else {
            *ival &= ~1;
        }
        break;
    case NUT_IRQCTL_ENABLE:
        enabled = 1;
        break;
    case NUT_IRQCTL_DISABLE:
        enabled = 0;
        break;
    case NUT_IRQCTL_GETMODE:
        {
            unsigned int val = inr(AIC_SMR(TC0_ID)) & AIC_SRCTYPE;
            if (val == AIC_SRCTYPE_INT_LEVEL_SENSITIVE || val == AIC_SRCTYPE_EXT_HIGH_LEVEL) {
                *ival = NUT_IRQMODE_LEVEL;
            } else {
                *ival = NUT_IRQMODE_EDGE;
            }
        }
        break;
    case NUT_IRQCTL_SETMODE:
        if (*ival == NUT_IRQMODE_LEVEL) {
            outr(AIC_SMR(TC0_ID), (inr(AIC_SMR(TC0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_LEVEL_SENSITIVE);
        } else if (*ival == NUT_IRQMODE_EDGE) {
            outr(AIC_SMR(TC0_ID), (inr(AIC_SMR(TC0_ID)) & ~AIC_SRCTYPE) | AIC_SRCTYPE_INT_EDGE_TRIGGERED);
        } else {
            rc = -1;
        }
        break;
    case NUT_IRQCTL_GETPRIO:
        *ival = inr(AIC_SMR(TC0_ID)) & AIC_PRIOR;
        break;
    case NUT_IRQCTL_SETPRIO:
        outr(AIC_SMR(TC0_ID), (inr(AIC_SMR(TC0_ID)) & ~AIC_PRIOR) | *ival);
        break;
#ifdef NUT_PERFMON
    case NUT_IRQCTL_GETCOUNT:
        *ival = (unsigned int) sig_TC0.ir_count;
        sig_TC0.ir_count = 0;
        break;
#endif
    default:
        rc = -1;
        break;
    }

    /* Enable interrupt. */
    if (enabled) {
        outr(AIC_IECR, _BV(TC0_ID));
    }
    return rc;
}