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Nut/OS
5.0.5
API Reference
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Nut/OS
5.0.5
API Reference
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00001 /**************************************************************************/ 00023 #if defined ( __ICCARM__ ) 00024 #pragma system_include /* treat file as system include file for MISRA check */ 00025 #endif 00026 00027 #ifdef __cplusplus 00028 extern "C" { 00029 #endif 00030 00031 #ifndef __CORE_CM3_H_GENERIC 00032 #define __CORE_CM3_H_GENERIC 00033 00048 /******************************************************************************* 00049 * CMSIS definitions 00050 ******************************************************************************/ 00055 /* CMSIS CM3 definitions */ 00056 #define __CM3_CMSIS_VERSION_MAIN (0x03) 00057 #define __CM3_CMSIS_VERSION_SUB (0x01) 00058 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \ 00059 __CM3_CMSIS_VERSION_SUB ) 00061 #define __CORTEX_M (0x03) 00064 #if defined ( __CC_ARM ) 00065 #define __ASM __asm 00066 #define __INLINE __inline 00067 #define __STATIC_INLINE static __inline 00068 00069 #elif defined ( __ICCARM__ ) 00070 #define __ASM __asm 00071 #define __INLINE inline 00072 #define __STATIC_INLINE static inline 00073 00074 #elif defined ( __TMS470__ ) 00075 #define __ASM __asm 00076 #define __STATIC_INLINE static inline 00077 00078 #elif defined ( __GNUC__ ) 00079 #define __ASM __asm 00080 #define __INLINE inline 00081 #define __STATIC_INLINE static inline 00082 00083 #elif defined ( __TASKING__ ) 00084 #define __ASM __asm 00085 #define __INLINE inline 00086 #define __STATIC_INLINE static inline 00087 00088 #endif 00089 00092 #define __FPU_USED 0 00093 00094 #if defined ( __CC_ARM ) 00095 #if defined __TARGET_FPU_VFP 00096 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00097 #endif 00098 00099 #elif defined ( __ICCARM__ ) 00100 #if defined __ARMVFP__ 00101 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00102 #endif 00103 00104 #elif defined ( __TMS470__ ) 00105 #if defined __TI__VFP_SUPPORT____ 00106 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00107 #endif 00108 00109 #elif defined ( __GNUC__ ) 00110 #if defined (__VFP_FP__) && !defined(__SOFTFP__) 00111 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" 00112 #endif 00113 00114 #elif defined ( __TASKING__ ) 00115 /* add preprocessor checks */ 00116 #endif 00117 00118 #include <stdint.h> /* standard types definitions */ 00119 #include <arch/cm3/core_cmInstr.h> /* Core Instruction Access */ 00120 #include <arch/cm3/core_cmFunc.h> /* Core Function Access */ 00121 00122 #endif /* __CORE_CM3_H_GENERIC */ 00123 00124 #ifndef __CMSIS_GENERIC 00125 00126 #ifndef __CORE_CM3_H_DEPENDANT 00127 #define __CORE_CM3_H_DEPENDANT 00128 00129 /* check device defines and use defaults */ 00130 #if defined __CHECK_DEVICE_DEFINES 00131 #ifndef __CM3_REV 00132 #define __CM3_REV 0x0200 00133 #warning "__CM3_REV not defined in device header file; using default!" 00134 #endif 00135 00136 #ifndef __MPU_PRESENT 00137 #define __MPU_PRESENT 0 00138 #warning "__MPU_PRESENT not defined in device header file; using default!" 00139 #endif 00140 00141 #ifndef __NVIC_PRIO_BITS 00142 #define __NVIC_PRIO_BITS 4 00143 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" 00144 #endif 00145 00146 #ifndef __Vendor_SysTickConfig 00147 #define __Vendor_SysTickConfig 0 00148 #warning "__Vendor_SysTickConfig not defined in device header file; using default!" 00149 #endif 00150 #endif 00151 00152 /* IO definitions (access restrictions to peripheral registers) */ 00160 #ifdef __cplusplus 00161 #define __I volatile 00162 #else 00163 #define __I volatile const 00164 #endif 00165 #define __O volatile 00166 #define __IO volatile 00168 00172 /******************************************************************************* 00173 * Register Abstraction 00174 Core Register contain: 00175 - Core Register 00176 - Core NVIC Register 00177 - Core SCB Register 00178 - Core SysTick Register 00179 - Core Debug Register 00180 - Core MPU Register 00181 ******************************************************************************/ 00182 00194 typedef union 00195 { 00196 struct 00197 { 00198 #if (__CORTEX_M != 0x04) 00199 uint32_t _reserved0:27; 00200 #else 00201 uint32_t _reserved0:16; 00202 uint32_t GE:4; 00203 uint32_t _reserved1:7; 00204 #endif 00205 uint32_t Q:1; 00206 uint32_t V:1; 00207 uint32_t C:1; 00208 uint32_t Z:1; 00209 uint32_t N:1; 00210 } b; 00211 uint32_t w; 00212 } APSR_Type; 00213 00214 00217 typedef union 00218 { 00219 struct 00220 { 00221 uint32_t ISR:9; 00222 uint32_t _reserved0:23; 00223 } b; 00224 uint32_t w; 00225 } IPSR_Type; 00226 00227 00230 typedef union 00231 { 00232 struct 00233 { 00234 uint32_t ISR:9; 00235 #if (__CORTEX_M != 0x04) 00236 uint32_t _reserved0:15; 00237 #else 00238 uint32_t _reserved0:7; 00239 uint32_t GE:4; 00240 uint32_t _reserved1:4; 00241 #endif 00242 uint32_t T:1; 00243 uint32_t IT:2; 00244 uint32_t Q:1; 00245 uint32_t V:1; 00246 uint32_t C:1; 00247 uint32_t Z:1; 00248 uint32_t N:1; 00249 } b; 00250 uint32_t w; 00251 } xPSR_Type; 00252 00253 00256 typedef union 00257 { 00258 struct 00259 { 00260 uint32_t nPRIV:1; 00261 uint32_t SPSEL:1; 00262 uint32_t FPCA:1; 00263 uint32_t _reserved0:29; 00264 } b; 00265 uint32_t w; 00266 } CONTROL_Type; 00267 00279 typedef struct 00280 { 00281 __IO uint32_t ISER[8]; 00282 uint32_t RESERVED0[24]; 00283 __IO uint32_t ICER[8]; 00284 uint32_t RSERVED1[24]; 00285 __IO uint32_t ISPR[8]; 00286 uint32_t RESERVED2[24]; 00287 __IO uint32_t ICPR[8]; 00288 uint32_t RESERVED3[24]; 00289 __IO uint32_t IABR[8]; 00290 uint32_t RESERVED4[56]; 00291 __IO uint8_t IP[240]; 00292 uint32_t RESERVED5[644]; 00293 __O uint32_t STIR; 00294 } NVIC_Type; 00295 00296 /* Software Triggered Interrupt Register Definitions */ 00297 #define NVIC_STIR_INTID_Pos 0 00298 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) 00300 00311 typedef struct 00312 { 00313 __I uint32_t CPUID; 00314 __IO uint32_t ICSR; 00315 __IO uint32_t VTOR; 00316 __IO uint32_t AIRCR; 00317 __IO uint32_t SCR; 00318 __IO uint32_t CCR; 00319 __IO uint8_t SHP[12]; 00320 __IO uint32_t SHCSR; 00321 __IO uint32_t CFSR; 00322 __IO uint32_t HFSR; 00323 __IO uint32_t DFSR; 00324 __IO uint32_t MMFAR; 00325 __IO uint32_t BFAR; 00326 __IO uint32_t AFSR; 00327 __I uint32_t PFR[2]; 00328 __I uint32_t DFR; 00329 __I uint32_t ADR; 00330 __I uint32_t MMFR[4]; 00331 __I uint32_t ISAR[5]; 00332 uint32_t RESERVED0[5]; 00333 __IO uint32_t CPACR; 00334 } SCB_Type; 00335 00336 /* SCB CPUID Register Definitions */ 00337 #define SCB_CPUID_IMPLEMENTER_Pos 24 00338 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) 00340 #define SCB_CPUID_VARIANT_Pos 20 00341 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) 00343 #define SCB_CPUID_ARCHITECTURE_Pos 16 00344 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) 00346 #define SCB_CPUID_PARTNO_Pos 4 00347 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) 00349 #define SCB_CPUID_REVISION_Pos 0 00350 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) 00352 /* SCB Interrupt Control State Register Definitions */ 00353 #define SCB_ICSR_NMIPENDSET_Pos 31 00354 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) 00356 #define SCB_ICSR_PENDSVSET_Pos 28 00357 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) 00359 #define SCB_ICSR_PENDSVCLR_Pos 27 00360 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) 00362 #define SCB_ICSR_PENDSTSET_Pos 26 00363 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) 00365 #define SCB_ICSR_PENDSTCLR_Pos 25 00366 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) 00368 #define SCB_ICSR_ISRPREEMPT_Pos 23 00369 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) 00371 #define SCB_ICSR_ISRPENDING_Pos 22 00372 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) 00374 #define SCB_ICSR_VECTPENDING_Pos 12 00375 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) 00377 #define SCB_ICSR_RETTOBASE_Pos 11 00378 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) 00380 #define SCB_ICSR_VECTACTIVE_Pos 0 00381 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) 00383 /* SCB Vector Table Offset Register Definitions */ 00384 #if (__CM3_REV < 0x0201) /* core r2p1 */ 00385 #define SCB_VTOR_TBLBASE_Pos 29 00386 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) 00388 #define SCB_VTOR_TBLOFF_Pos 7 00389 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) 00390 #else 00391 #define SCB_VTOR_TBLOFF_Pos 7 00392 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) 00393 #endif 00394 00395 /* SCB Application Interrupt and Reset Control Register Definitions */ 00396 #define SCB_AIRCR_VECTKEY_Pos 16 00397 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) 00399 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 00400 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) 00402 #define SCB_AIRCR_ENDIANESS_Pos 15 00403 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) 00405 #define SCB_AIRCR_PRIGROUP_Pos 8 00406 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) 00408 #define SCB_AIRCR_SYSRESETREQ_Pos 2 00409 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) 00411 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 00412 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) 00414 #define SCB_AIRCR_VECTRESET_Pos 0 00415 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) 00417 /* SCB System Control Register Definitions */ 00418 #define SCB_SCR_SEVONPEND_Pos 4 00419 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) 00421 #define SCB_SCR_SLEEPDEEP_Pos 2 00422 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) 00424 #define SCB_SCR_SLEEPONEXIT_Pos 1 00425 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) 00427 /* SCB Configuration Control Register Definitions */ 00428 #define SCB_CCR_STKALIGN_Pos 9 00429 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) 00431 #define SCB_CCR_BFHFNMIGN_Pos 8 00432 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) 00434 #define SCB_CCR_DIV_0_TRP_Pos 4 00435 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) 00437 #define SCB_CCR_UNALIGN_TRP_Pos 3 00438 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) 00440 #define SCB_CCR_USERSETMPEND_Pos 1 00441 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) 00443 #define SCB_CCR_NONBASETHRDENA_Pos 0 00444 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) 00446 /* SCB System Handler Control and State Register Definitions */ 00447 #define SCB_SHCSR_USGFAULTENA_Pos 18 00448 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) 00450 #define SCB_SHCSR_BUSFAULTENA_Pos 17 00451 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) 00453 #define SCB_SHCSR_MEMFAULTENA_Pos 16 00454 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) 00456 #define SCB_SHCSR_SVCALLPENDED_Pos 15 00457 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) 00459 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 00460 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) 00462 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 00463 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) 00465 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 00466 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) 00468 #define SCB_SHCSR_SYSTICKACT_Pos 11 00469 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) 00471 #define SCB_SHCSR_PENDSVACT_Pos 10 00472 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) 00474 #define SCB_SHCSR_MONITORACT_Pos 8 00475 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) 00477 #define SCB_SHCSR_SVCALLACT_Pos 7 00478 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) 00480 #define SCB_SHCSR_USGFAULTACT_Pos 3 00481 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) 00483 #define SCB_SHCSR_BUSFAULTACT_Pos 1 00484 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) 00486 #define SCB_SHCSR_MEMFAULTACT_Pos 0 00487 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) 00489 /* SCB Configurable Fault Status Registers Definitions */ 00490 #define SCB_CFSR_USGFAULTSR_Pos 16 00491 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) 00493 #define SCB_CFSR_BUSFAULTSR_Pos 8 00494 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) 00496 #define SCB_CFSR_MEMFAULTSR_Pos 0 00497 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) 00499 /* SCB Hard Fault Status Registers Definitions */ 00500 #define SCB_HFSR_DEBUGEVT_Pos 31 00501 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) 00503 #define SCB_HFSR_FORCED_Pos 30 00504 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) 00506 #define SCB_HFSR_VECTTBL_Pos 1 00507 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) 00509 /* SCB Debug Fault Status Register Definitions */ 00510 #define SCB_DFSR_EXTERNAL_Pos 4 00511 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) 00513 #define SCB_DFSR_VCATCH_Pos 3 00514 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) 00516 #define SCB_DFSR_DWTTRAP_Pos 2 00517 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) 00519 #define SCB_DFSR_BKPT_Pos 1 00520 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) 00522 #define SCB_DFSR_HALTED_Pos 0 00523 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) 00525 00536 typedef struct 00537 { 00538 uint32_t RESERVED0[1]; 00539 __I uint32_t ICTR; 00540 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200)) 00541 __IO uint32_t ACTLR; 00542 #else 00543 uint32_t RESERVED1[1]; 00544 #endif 00545 } SCnSCB_Type; 00546 00547 /* Interrupt Controller Type Register Definitions */ 00548 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 00549 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) 00551 /* Auxiliary Control Register Definitions */ 00552 00553 #define SCnSCB_ACTLR_DISFOLD_Pos 2 00554 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) 00556 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 00557 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) 00559 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 00560 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) 00562 00573 typedef struct 00574 { 00575 __IO uint32_t CTRL; 00576 __IO uint32_t LOAD; 00577 __IO uint32_t VAL; 00578 __I uint32_t CALIB; 00579 } SysTick_Type; 00580 00581 /* SysTick Control / Status Register Definitions */ 00582 #define SysTick_CTRL_COUNTFLAG_Pos 16 00583 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) 00585 #define SysTick_CTRL_CLKSOURCE_Pos 2 00586 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) 00588 #define SysTick_CTRL_TICKINT_Pos 1 00589 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) 00591 #define SysTick_CTRL_ENABLE_Pos 0 00592 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) 00594 /* SysTick Reload Register Definitions */ 00595 #define SysTick_LOAD_RELOAD_Pos 0 00596 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) 00598 /* SysTick Current Register Definitions */ 00599 #define SysTick_VAL_CURRENT_Pos 0 00600 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) 00602 /* SysTick Calibration Register Definitions */ 00603 #define SysTick_CALIB_NOREF_Pos 31 00604 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) 00606 #define SysTick_CALIB_SKEW_Pos 30 00607 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) 00609 #define SysTick_CALIB_TENMS_Pos 0 00610 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) 00612 00623 typedef struct 00624 { 00625 __O union 00626 { 00627 __O uint8_t u8; 00628 __O uint16_t u16; 00629 __O uint32_t u32; 00630 } PORT [32]; 00631 uint32_t RESERVED0[864]; 00632 __IO uint32_t TER; 00633 uint32_t RESERVED1[15]; 00634 __IO uint32_t TPR; 00635 uint32_t RESERVED2[15]; 00636 __IO uint32_t TCR; 00637 } ITM_Type; 00638 00639 /* ITM Trace Privilege Register Definitions */ 00640 #define ITM_TPR_PRIVMASK_Pos 0 00641 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) 00643 /* ITM Trace Control Register Definitions */ 00644 #define ITM_TCR_BUSY_Pos 23 00645 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) 00647 #define ITM_TCR_TraceBusID_Pos 16 00648 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) 00650 #define ITM_TCR_GTSFREQ_Pos 10 00651 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) 00653 #define ITM_TCR_TSPrescale_Pos 8 00654 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) 00656 #define ITM_TCR_SWOENA_Pos 4 00657 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) 00659 #define ITM_TCR_TXENA_Pos 3 00660 #define ITM_TCR_TXENA_Msk (1UL << ITM_TCR_TXENA_Pos) 00662 #define ITM_TCR_SYNCENA_Pos 2 00663 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) 00665 #define ITM_TCR_TSENA_Pos 1 00666 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) 00668 #define ITM_TCR_ITMENA_Pos 0 00669 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) 00671 /* end of group CMSIS_ITM */ 00672 00673 00682 typedef struct 00683 { 00684 __IO uint32_t CTRL; 00685 __IO uint32_t CYCCNT; 00686 __IO uint32_t CPICNT; 00687 __IO uint32_t EXCCNT; 00688 __IO uint32_t SLEEPCNT; 00689 __IO uint32_t LSUCNT; 00690 __IO uint32_t FOLDCNT; 00691 __I uint32_t PCSR; 00692 __IO uint32_t COMP0; 00693 __IO uint32_t MASK0; 00694 __IO uint32_t FUNCTION0; 00695 uint32_t RESERVED0[1]; 00696 __IO uint32_t COMP1; 00697 __IO uint32_t MASK1; 00698 __IO uint32_t FUNCTION1; 00699 uint32_t RESERVED1[1]; 00700 __IO uint32_t COMP2; 00701 __IO uint32_t MASK2; 00702 __IO uint32_t FUNCTION2; 00703 uint32_t RESERVED2[1]; 00704 __IO uint32_t COMP3; 00705 __IO uint32_t MASK3; 00706 __IO uint32_t FUNCTION3; 00707 } DWT_Type; 00708 00709 /* DWT Control Register Definitions */ 00710 #define DWT_CTRL_NUMCOMP_Pos 28 00711 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) 00713 #define DWT_CTRL_NOTRCPKT_Pos 27 00714 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) 00716 #define DWT_CTRL_NOEXTTRIG_Pos 26 00717 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) 00719 #define DWT_CTRL_NOCYCCNT_Pos 25 00720 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) 00722 #define DWT_CTRL_NOPRFCNT_Pos 24 00723 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) 00725 #define DWT_CTRL_CYCEVTENA_Pos 22 00726 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) 00728 #define DWT_CTRL_FOLDEVTENA_Pos 21 00729 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) 00731 #define DWT_CTRL_LSUEVTENA_Pos 20 00732 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) 00734 #define DWT_CTRL_SLEEPEVTENA_Pos 19 00735 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) 00737 #define DWT_CTRL_EXCEVTENA_Pos 18 00738 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) 00740 #define DWT_CTRL_CPIEVTENA_Pos 17 00741 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) 00743 #define DWT_CTRL_EXCTRCENA_Pos 16 00744 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) 00746 #define DWT_CTRL_PCSAMPLENA_Pos 12 00747 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) 00749 #define DWT_CTRL_SYNCTAP_Pos 10 00750 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) 00752 #define DWT_CTRL_CYCTAP_Pos 9 00753 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) 00755 #define DWT_CTRL_POSTINIT_Pos 5 00756 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) 00758 #define DWT_CTRL_POSTPRESET_Pos 1 00759 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) 00761 #define DWT_CTRL_CYCCNTENA_Pos 0 00762 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) 00764 /* DWT CPI Count Register Definitions */ 00765 #define DWT_CPICNT_CPICNT_Pos 0 00766 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) 00768 /* DWT Exception Overhead Count Register Definitions */ 00769 #define DWT_EXCCNT_EXCCNT_Pos 0 00770 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) 00772 /* DWT Sleep Count Register Definitions */ 00773 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 00774 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) 00776 /* DWT LSU Count Register Definitions */ 00777 #define DWT_LSUCNT_LSUCNT_Pos 0 00778 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) 00780 /* DWT Folded-instruction Count Register Definitions */ 00781 #define DWT_FOLDCNT_FOLDCNT_Pos 0 00782 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) 00784 /* DWT Comparator Mask Register Definitions */ 00785 #define DWT_MASK_MASK_Pos 0 00786 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) 00788 /* DWT Comparator Function Register Definitions */ 00789 #define DWT_FUNCTION_MATCHED_Pos 24 00790 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) 00792 #define DWT_FUNCTION_DATAVADDR1_Pos 16 00793 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) 00795 #define DWT_FUNCTION_DATAVADDR0_Pos 12 00796 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) 00798 #define DWT_FUNCTION_DATAVSIZE_Pos 10 00799 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) 00801 #define DWT_FUNCTION_LNK1ENA_Pos 9 00802 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) 00804 #define DWT_FUNCTION_DATAVMATCH_Pos 8 00805 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) 00807 #define DWT_FUNCTION_CYCMATCH_Pos 7 00808 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) 00810 #define DWT_FUNCTION_EMITRANGE_Pos 5 00811 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) 00813 #define DWT_FUNCTION_FUNCTION_Pos 0 00814 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) 00816 /* end of group CMSIS_DWT */ 00817 00818 00827 typedef struct 00828 { 00829 __IO uint32_t SSPSR; 00830 __IO uint32_t CSPSR; 00831 uint32_t RESERVED0[2]; 00832 __IO uint32_t ACPR; 00833 uint32_t RESERVED1[55]; 00834 __IO uint32_t SPPR; 00835 uint32_t RESERVED2[131]; 00836 __I uint32_t FFSR; 00837 __IO uint32_t FFCR; 00838 __I uint32_t FSCR; 00839 uint32_t RESERVED3[759]; 00840 __I uint32_t TRIGGER; 00841 __I uint32_t FIFO0; 00842 __I uint32_t ITATBCTR2; 00843 uint32_t RESERVED4[1]; 00844 __I uint32_t ITATBCTR0; 00845 __I uint32_t FIFO1; 00846 __IO uint32_t ITCTRL; 00847 uint32_t RESERVED5[39]; 00848 __IO uint32_t CLAIMSET; 00849 __IO uint32_t CLAIMCLR; 00850 uint32_t RESERVED7[8]; 00851 __I uint32_t DEVID; 00852 __I uint32_t DEVTYPE; 00853 } TPI_Type; 00854 00855 /* TPI Asynchronous Clock Prescaler Register Definitions */ 00856 #define TPI_ACPR_PRESCALER_Pos 0 00857 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) 00859 /* TPI Selected Pin Protocol Register Definitions */ 00860 #define TPI_SPPR_TXMODE_Pos 0 00861 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) 00863 /* TPI Formatter and Flush Status Register Definitions */ 00864 #define TPI_FFSR_FtNonStop_Pos 3 00865 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) 00867 #define TPI_FFSR_TCPresent_Pos 2 00868 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) 00870 #define TPI_FFSR_FtStopped_Pos 1 00871 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) 00873 #define TPI_FFSR_FlInProg_Pos 0 00874 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) 00876 /* TPI Formatter and Flush Control Register Definitions */ 00877 #define TPI_FFCR_TrigIn_Pos 8 00878 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) 00880 #define TPI_FFCR_EnFCont_Pos 1 00881 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) 00883 /* TPI TRIGGER Register Definitions */ 00884 #define TPI_TRIGGER_TRIGGER_Pos 0 00885 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) 00887 /* TPI Integration ETM Data Register Definitions (FIFO0) */ 00888 #define TPI_FIFO0_ITM_ATVALID_Pos 29 00889 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) 00891 #define TPI_FIFO0_ITM_bytecount_Pos 27 00892 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) 00894 #define TPI_FIFO0_ETM_ATVALID_Pos 26 00895 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) 00897 #define TPI_FIFO0_ETM_bytecount_Pos 24 00898 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) 00900 #define TPI_FIFO0_ETM2_Pos 16 00901 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) 00903 #define TPI_FIFO0_ETM1_Pos 8 00904 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) 00906 #define TPI_FIFO0_ETM0_Pos 0 00907 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) 00909 /* TPI ITATBCTR2 Register Definitions */ 00910 #define TPI_ITATBCTR2_ATREADY_Pos 0 00911 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) 00913 /* TPI Integration ITM Data Register Definitions (FIFO1) */ 00914 #define TPI_FIFO1_ITM_ATVALID_Pos 29 00915 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) 00917 #define TPI_FIFO1_ITM_bytecount_Pos 27 00918 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) 00920 #define TPI_FIFO1_ETM_ATVALID_Pos 26 00921 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) 00923 #define TPI_FIFO1_ETM_bytecount_Pos 24 00924 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) 00926 #define TPI_FIFO1_ITM2_Pos 16 00927 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) 00929 #define TPI_FIFO1_ITM1_Pos 8 00930 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) 00932 #define TPI_FIFO1_ITM0_Pos 0 00933 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) 00935 /* TPI ITATBCTR0 Register Definitions */ 00936 #define TPI_ITATBCTR0_ATREADY_Pos 0 00937 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) 00939 /* TPI Integration Mode Control Register Definitions */ 00940 #define TPI_ITCTRL_Mode_Pos 0 00941 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) 00943 /* TPI DEVID Register Definitions */ 00944 #define TPI_DEVID_NRZVALID_Pos 11 00945 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) 00947 #define TPI_DEVID_MANCVALID_Pos 10 00948 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) 00950 #define TPI_DEVID_PTINVALID_Pos 9 00951 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) 00953 #define TPI_DEVID_MinBufSz_Pos 6 00954 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) 00956 #define TPI_DEVID_AsynClkIn_Pos 5 00957 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) 00959 #define TPI_DEVID_NrTraceInput_Pos 0 00960 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) 00962 /* TPI DEVTYPE Register Definitions */ 00963 #define TPI_DEVTYPE_SubType_Pos 0 00964 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) 00966 #define TPI_DEVTYPE_MajorType_Pos 4 00967 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) 00969 /* end of group CMSIS_TPI */ 00970 00971 00972 #if (__MPU_PRESENT == 1) 00973 00981 typedef struct 00982 { 00983 __I uint32_t TYPE; 00984 __IO uint32_t CTRL; 00985 __IO uint32_t RNR; 00986 __IO uint32_t RBAR; 00987 __IO uint32_t RASR; 00988 __IO uint32_t RBAR_A1; 00989 __IO uint32_t RASR_A1; 00990 __IO uint32_t RBAR_A2; 00991 __IO uint32_t RASR_A2; 00992 __IO uint32_t RBAR_A3; 00993 __IO uint32_t RASR_A3; 00994 } MPU_Type; 00995 00996 /* MPU Type Register */ 00997 #define MPU_TYPE_IREGION_Pos 16 00998 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) 01000 #define MPU_TYPE_DREGION_Pos 8 01001 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) 01003 #define MPU_TYPE_SEPARATE_Pos 0 01004 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) 01006 /* MPU Control Register */ 01007 #define MPU_CTRL_PRIVDEFENA_Pos 2 01008 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) 01010 #define MPU_CTRL_HFNMIENA_Pos 1 01011 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) 01013 #define MPU_CTRL_ENABLE_Pos 0 01014 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) 01016 /* MPU Region Number Register */ 01017 #define MPU_RNR_REGION_Pos 0 01018 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) 01020 /* MPU Region Base Address Register */ 01021 #define MPU_RBAR_ADDR_Pos 5 01022 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) 01024 #define MPU_RBAR_VALID_Pos 4 01025 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) 01027 #define MPU_RBAR_REGION_Pos 0 01028 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) 01030 /* MPU Region Attribute and Size Register */ 01031 #define MPU_RASR_ATTRS_Pos 16 01032 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) 01034 #define MPU_RASR_SRD_Pos 8 01035 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) 01037 #define MPU_RASR_SIZE_Pos 1 01038 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) 01040 #define MPU_RASR_ENABLE_Pos 0 01041 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) 01043 01044 #endif 01045 01046 01055 typedef struct 01056 { 01057 __IO uint32_t DHCSR; 01058 __O uint32_t DCRSR; 01059 __IO uint32_t DCRDR; 01060 __IO uint32_t DEMCR; 01061 } CoreDebug_Type; 01062 01063 /* Debug Halting Control and Status Register */ 01064 #define CoreDebug_DHCSR_DBGKEY_Pos 16 01065 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) 01067 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 01068 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) 01070 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 01071 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) 01073 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 01074 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) 01076 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 01077 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) 01079 #define CoreDebug_DHCSR_S_HALT_Pos 17 01080 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) 01082 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 01083 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) 01085 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 01086 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) 01088 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 01089 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) 01091 #define CoreDebug_DHCSR_C_STEP_Pos 2 01092 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) 01094 #define CoreDebug_DHCSR_C_HALT_Pos 1 01095 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) 01097 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 01098 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) 01100 /* Debug Core Register Selector Register */ 01101 #define CoreDebug_DCRSR_REGWnR_Pos 16 01102 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) 01104 #define CoreDebug_DCRSR_REGSEL_Pos 0 01105 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) 01107 /* Debug Exception and Monitor Control Register */ 01108 #define CoreDebug_DEMCR_TRCENA_Pos 24 01109 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) 01111 #define CoreDebug_DEMCR_MON_REQ_Pos 19 01112 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) 01114 #define CoreDebug_DEMCR_MON_STEP_Pos 18 01115 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) 01117 #define CoreDebug_DEMCR_MON_PEND_Pos 17 01118 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) 01120 #define CoreDebug_DEMCR_MON_EN_Pos 16 01121 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) 01123 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 01124 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) 01126 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 01127 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) 01129 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 01130 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) 01132 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 01133 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) 01135 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 01136 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) 01138 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 01139 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) 01141 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 01142 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) 01144 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 01145 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) 01147 01156 /* Memory mapping of Cortex-M3 Hardware */ 01157 #define SCS_BASE (0xE000E000UL) 01158 #define ITM_BASE (0xE0000000UL) 01159 #define DWT_BASE (0xE0001000UL) 01160 #define TPI_BASE (0xE0040000UL) 01161 #define CoreDebug_BASE (0xE000EDF0UL) 01162 #define SysTick_BASE (SCS_BASE + 0x0010UL) 01163 #define NVIC_BASE (SCS_BASE + 0x0100UL) 01164 #define SCB_BASE (SCS_BASE + 0x0D00UL) 01166 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) 01167 #define SCB ((SCB_Type *) SCB_BASE ) 01168 #define SysTick ((SysTick_Type *) SysTick_BASE ) 01169 #define NVIC ((NVIC_Type *) NVIC_BASE ) 01170 #define ITM ((ITM_Type *) ITM_BASE ) 01171 #define DWT ((DWT_Type *) DWT_BASE ) 01172 #define TPI ((TPI_Type *) TPI_BASE ) 01173 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) 01175 #if (__MPU_PRESENT == 1) 01176 #define MPU_BASE (SCS_BASE + 0x0D90UL) 01177 #define MPU ((MPU_Type *) MPU_BASE ) 01178 #endif 01179 01184 /******************************************************************************* 01185 * Hardware Abstraction Layer 01186 Core Function Interface contains: 01187 - Core NVIC Functions 01188 - Core SysTick Functions 01189 - Core Debug Functions 01190 - Core Register Access Functions 01191 ******************************************************************************/ 01197 /* ########################## NVIC functions #################################### */ 01214 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 01215 { 01216 uint32_t reg_value; 01217 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */ 01218 01219 reg_value = SCB->AIRCR; /* read old register configuration */ 01220 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */ 01221 reg_value = (reg_value | 01222 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) | 01223 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */ 01224 SCB->AIRCR = reg_value; 01225 } 01226 01227 01234 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void) 01235 { 01236 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */ 01237 } 01238 01239 01246 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) 01247 { 01248 NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */ 01249 } 01250 01251 01258 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) 01259 { 01260 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */ 01261 } 01262 01263 01274 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) 01275 { 01276 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */ 01277 } 01278 01279 01286 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) 01287 { 01288 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */ 01289 } 01290 01291 01298 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) 01299 { 01300 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */ 01301 } 01302 01303 01313 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) 01314 { 01315 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */ 01316 } 01317 #define NVIC_GetEnableIRQ NVIC_GetActive 01318 01319 01329 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) 01330 { 01331 if(IRQn < 0) { 01332 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */ 01333 else { 01334 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */ 01335 } 01336 01337 01349 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) 01350 { 01351 01352 if(IRQn < 0) { 01353 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */ 01354 else { 01355 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */ 01356 } 01357 01358 01371 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) 01372 { 01373 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 01374 uint32_t PreemptPriorityBits; 01375 uint32_t SubPriorityBits; 01376 01377 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 01378 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 01379 01380 return ( 01381 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) | 01382 ((SubPriority & ((1 << (SubPriorityBits )) - 1))) 01383 ); 01384 } 01385 01386 01399 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority) 01400 { 01401 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */ 01402 uint32_t PreemptPriorityBits; 01403 uint32_t SubPriorityBits; 01404 01405 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp; 01406 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS; 01407 01408 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1); 01409 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1); 01410 } 01411 01412 01417 __STATIC_INLINE void NVIC_SystemReset(void) 01418 { 01419 __DSB(); /* Ensure all outstanding memory accesses included 01420 buffered write are completed before reset */ 01421 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) | 01422 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | 01423 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */ 01424 __DSB(); /* Ensure completion of memory access */ 01425 while(1); /* wait until reset */ 01426 } 01427 01432 /* ################################## SysTick function ############################################ */ 01439 #if (__Vendor_SysTickConfig == 0) 01440 01456 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) 01457 { 01458 if (ticks > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */ 01459 01460 SysTick->LOAD = (ticks & SysTick_LOAD_RELOAD_Msk) - 1; /* set reload register */ 01461 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */ 01462 SysTick->VAL = 0; /* Load the SysTick Counter Value */ 01463 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | 01464 SysTick_CTRL_TICKINT_Msk | 01465 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ 01466 return (0); /* Function successful */ 01467 } 01468 01469 #endif 01470 01475 /* ##################################### Debug In/Output function ########################################### */ 01482 extern volatile int32_t ITM_RxBuffer; 01483 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 01496 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) 01497 { 01498 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */ 01499 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */ 01500 { 01501 while (ITM->PORT[0].u32 == 0); 01502 ITM->PORT[0].u8 = (uint8_t) ch; 01503 } 01504 return (ch); 01505 } 01506 01507 01515 __STATIC_INLINE int32_t ITM_ReceiveChar (void) { 01516 int32_t ch = -1; /* no character available */ 01517 01518 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) { 01519 ch = ITM_RxBuffer; 01520 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ 01521 } 01522 01523 return (ch); 01524 } 01525 01526 01534 __STATIC_INLINE int32_t ITM_CheckChar (void) { 01535 01536 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) { 01537 return (0); /* no character available */ 01538 } else { 01539 return (1); /* character available */ 01540 } 01541 } 01542 01545 #endif /* __CORE_CM3_H_DEPENDANT */ 01546 01547 #endif /* __CMSIS_GENERIC */ 01548 01549 #ifdef __cplusplus 01550 } 01551 #endif