lpc177x_8x.h File Reference

Cortex-M3 Core Peripheral Access Layer Header File for NXP LPC177x_8x Series. More...

#include <arch/cm3/core_cm3.h>
#include "system_lpc177x_8x.h"

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Data Structures
struct	LPC_SC_TypeDef
struct	LPC_IOCON_TypeDef
struct	LPC_GPIO_TypeDef
struct	LPC_GPIOINT_TypeDef
struct	LPC_TIM_TypeDef
struct	LPC_PWM_TypeDef
struct	LPC_UART_TypeDef
struct	LPC_UART1_TypeDef
struct	LPC_UART4_TypeDef
struct	LPC_SSP_TypeDef
struct	LPC_I2C_TypeDef
struct	LPC_I2S_TypeDef
struct	LPC_RTC_TypeDef
struct	LPC_WDT_TypeDef
struct	LPC_ADC_TypeDef
struct	LPC_DAC_TypeDef
struct	LPC_MCPWM_TypeDef
struct	LPC_QEI_TypeDef
struct	LPC_MCI_TypeDef
struct	LPC_CANAF_RAM_TypeDef
struct	LPC_CANAF_TypeDef
struct	LPC_CANCR_TypeDef
struct	LPC_CAN_TypeDef
struct	LPC_GPDMA_TypeDef
struct	LPC_GPDMACH_TypeDef
struct	LPC_USB_TypeDef
struct	LPC_EMAC_TypeDef
struct	LPC_LCD_TypeDef
struct	LPC_EMC_TypeDef
struct	LPC_CRC_TypeDef
struct	LPC_EEPROM_TypeDef
Defines
#define	__MPU_PRESENT   1
#define	__NVIC_PRIO_BITS   5
#define	__Vendor_SysTickConfig   0
#define	LPC_FLASH_BASE   (0x00000000UL)
#define	LPC_RAM_BASE   (0x10000000UL)
#define	LPC_PERI_RAM_BASE   (0x20000000UL)
#define	LPC_APB0_BASE   (0x40000000UL)
#define	LPC_APB1_BASE   (0x40080000UL)
#define	LPC_AHBRAM1_BASE   (0x20004000UL)
#define	LPC_AHB_BASE   (0x20080000UL)
#define	LPC_CM3_BASE   (0xE0000000UL)
#define	LPC_WDT_BASE   (LPC_APB0_BASE + 0x00000)
#define	LPC_TIM0_BASE   (LPC_APB0_BASE + 0x04000)
#define	LPC_TIM1_BASE   (LPC_APB0_BASE + 0x08000)
#define	LPC_UART0_BASE   (LPC_APB0_BASE + 0x0C000)
#define	LPC_UART1_BASE   (LPC_APB0_BASE + 0x10000)
#define	LPC_PWM0_BASE   (LPC_APB0_BASE + 0x14000)
#define	LPC_PWM1_BASE   (LPC_APB0_BASE + 0x18000)
#define	LPC_I2C0_BASE   (LPC_APB0_BASE + 0x1C000)
#define	LPC_RTC_BASE   (LPC_APB0_BASE + 0x24000)
#define	LPC_GPIOINT_BASE   (LPC_APB0_BASE + 0x28080)
#define	LPC_IOCON_BASE   (LPC_APB0_BASE + 0x2C000)
#define	LPC_SSP1_BASE   (LPC_APB0_BASE + 0x30000)
#define	LPC_ADC_BASE   (LPC_APB0_BASE + 0x34000)
#define	LPC_CANAF_RAM_BASE   (LPC_APB0_BASE + 0x38000)
#define	LPC_CANAF_BASE   (LPC_APB0_BASE + 0x3C000)
#define	LPC_CANCR_BASE   (LPC_APB0_BASE + 0x40000)
#define	LPC_CAN1_BASE   (LPC_APB0_BASE + 0x44000)
#define	LPC_CAN2_BASE   (LPC_APB0_BASE + 0x48000)
#define	LPC_I2C1_BASE   (LPC_APB0_BASE + 0x5C000)
#define	LPC_SSP0_BASE   (LPC_APB1_BASE + 0x08000)
#define	LPC_DAC_BASE   (LPC_APB1_BASE + 0x0C000)
#define	LPC_TIM2_BASE   (LPC_APB1_BASE + 0x10000)
#define	LPC_TIM3_BASE   (LPC_APB1_BASE + 0x14000)
#define	LPC_UART2_BASE   (LPC_APB1_BASE + 0x18000)
#define	LPC_UART3_BASE   (LPC_APB1_BASE + 0x1C000)
#define	LPC_I2C2_BASE   (LPC_APB1_BASE + 0x20000)
#define	LPC_UART4_BASE   (LPC_APB1_BASE + 0x24000)
#define	LPC_I2S_BASE   (LPC_APB1_BASE + 0x28000)
#define	LPC_SSP2_BASE   (LPC_APB1_BASE + 0x2C000)
#define	LPC_MCPWM_BASE   (LPC_APB1_BASE + 0x38000)
#define	LPC_QEI_BASE   (LPC_APB1_BASE + 0x3C000)
#define	LPC_MCI_BASE   (LPC_APB1_BASE + 0x40000)
#define	LPC_SC_BASE   (LPC_APB1_BASE + 0x7C000)
#define	LPC_GPDMA_BASE   (LPC_AHB_BASE + 0x00000)
#define	LPC_GPDMACH0_BASE   (LPC_AHB_BASE + 0x00100)
#define	LPC_GPDMACH1_BASE   (LPC_AHB_BASE + 0x00120)
#define	LPC_GPDMACH2_BASE   (LPC_AHB_BASE + 0x00140)
#define	LPC_GPDMACH3_BASE   (LPC_AHB_BASE + 0x00160)
#define	LPC_GPDMACH4_BASE   (LPC_AHB_BASE + 0x00180)
#define	LPC_GPDMACH5_BASE   (LPC_AHB_BASE + 0x001A0)
#define	LPC_GPDMACH6_BASE   (LPC_AHB_BASE + 0x001C0)
#define	LPC_GPDMACH7_BASE   (LPC_AHB_BASE + 0x001E0)
#define	LPC_EMAC_BASE   (LPC_AHB_BASE + 0x04000)
#define	LPC_LCD_BASE   (LPC_AHB_BASE + 0x08000)
#define	LPC_USB_BASE   (LPC_AHB_BASE + 0x0C000)
#define	LPC_CRC_BASE   (LPC_AHB_BASE + 0x10000)
#define	LPC_GPIO0_BASE   (LPC_AHB_BASE + 0x18000)
#define	LPC_GPIO1_BASE   (LPC_AHB_BASE + 0x18020)
#define	LPC_GPIO2_BASE   (LPC_AHB_BASE + 0x18040)
#define	LPC_GPIO3_BASE   (LPC_AHB_BASE + 0x18060)
#define	LPC_GPIO4_BASE   (LPC_AHB_BASE + 0x18080)
#define	LPC_GPIO5_BASE   (LPC_AHB_BASE + 0x180A0)
#define	LPC_EMC_BASE   (LPC_AHB_BASE + 0x1C000)
#define	LPC_EEPROM_BASE   (LPC_FLASH_BASE+ 0x200080)
#define	LPC_SC   ((LPC_SC_TypeDef *) LPC_SC_BASE )
#define	LPC_WDT   ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
#define	LPC_TIM0   ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
#define	LPC_TIM1   ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
#define	LPC_TIM2   ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
#define	LPC_TIM3   ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
#define	LPC_UART0   ((LPC_UART_TypeDef *) LPC_UART0_BASE )
#define	LPC_UART1   ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
#define	LPC_UART2   ((LPC_UART_TypeDef *) LPC_UART2_BASE )
#define	LPC_UART3   ((LPC_UART_TypeDef *) LPC_UART3_BASE )
#define	LPC_UART4   ((LPC_UART4_TypeDef *) LPC_UART4_BASE )
#define	LPC_PWM0   ((LPC_PWM_TypeDef *) LPC_PWM0_BASE )
#define	LPC_PWM1   ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
#define	LPC_I2C0   ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
#define	LPC_I2C1   ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
#define	LPC_I2C2   ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
#define	LPC_I2S   ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
#define	LPC_RTC   ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
#define	LPC_GPIOINT   ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
#define	LPC_IOCON   ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
#define	LPC_SSP0   ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
#define	LPC_SSP1   ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
#define	LPC_SSP2   ((LPC_SSP_TypeDef *) LPC_SSP2_BASE )
#define	LPC_ADC   ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
#define	LPC_DAC   ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
#define	LPC_CANAF_RAM   ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
#define	LPC_CANAF   ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
#define	LPC_CANCR   ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
#define	LPC_CAN1   ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
#define	LPC_CAN2   ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
#define	LPC_MCPWM   ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
#define	LPC_QEI   ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
#define	LPC_MCI   ((LPC_MCI_TypeDef *) LPC_MCI_BASE )
#define	LPC_GPDMA   ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
#define	LPC_GPDMACH0   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
#define	LPC_GPDMACH1   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
#define	LPC_GPDMACH2   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
#define	LPC_GPDMACH3   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
#define	LPC_GPDMACH4   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
#define	LPC_GPDMACH5   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
#define	LPC_GPDMACH6   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
#define	LPC_GPDMACH7   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
#define	LPC_EMAC   ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
#define	LPC_LCD   ((LPC_LCD_TypeDef *) LPC_LCD_BASE )
#define	LPC_USB   ((LPC_USB_TypeDef *) LPC_USB_BASE )
#define	LPC_GPIO0   ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
#define	LPC_GPIO1   ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
#define	LPC_GPIO2   ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
#define	LPC_GPIO3   ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
#define	LPC_GPIO4   ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
#define	LPC_GPIO5   ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE )
#define	LPC_EMC   ((LPC_EMC_TypeDef *) LPC_EMC_BASE )
#define	LPC_CRC   ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
#define	LPC_EEPROM   ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE )
Typedefs
typedef enum IRQn	IRQn_Type
Enumerations
enum	IRQn {   NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,   SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,   IROn_SUPC = AT91C_ID_SUPC, IROn_RSTC = AT91C_ID_RSTC, IROn_RTC = AT91C_ID_RTC, IROn_RTT = AT91C_ID_RTT,   IROn_WDG = AT91C_ID_WDG, IROn_PMC = AT91C_ID_PMC, IROn_EFC0 = AT91C_ID_EFC0, IROn_EFC1 = AT91C_ID_EFC1,   IROn_DBGU = AT91C_ID_DBGU, IROn_HSMC4 = AT91C_ID_HSMC4, IROn_PIOA = AT91C_ID_PIOA, IROn_PIOB = AT91C_ID_PIOB,   IROn_PIOC = AT91C_ID_PIOC, IROn_US0 = AT91C_ID_US0, IROn_US1 = AT91C_ID_US1, IROn_US2 = AT91C_ID_US2,   IROn_US3 = AT91C_ID_US3, IROn_MCI0 = AT91C_ID_MCI0, IROn_TWI0 = AT91C_ID_TWI0, IROn_TWI1 = AT91C_ID_TWI1,   IROn_SPI0 = AT91C_ID_SPI0, IROn_SSC0 = AT91C_ID_SSC0, IROn_TC0 = AT91C_ID_TC0, IROn_TC1 = AT91C_ID_TC1,   IROn_TC2 = AT91C_ID_TC2, IROn_PWMC = AT91C_ID_PWMC, IROn_ADCC0 = AT91C_ID_ADCC0, IROn_ADCC1 = AT91C_ID_ADCC1,   IROn_HDMA = AT91C_ID_HDMA, IROn_UDPHS = AT91C_ID_UDPHS, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13,   MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5,   DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, WDT_IRQn = 0,   TIMER0_IRQn = 1, TIMER1_IRQn = 2, TIMER2_IRQn = 3, TIMER3_IRQn = 4,   UART0_IRQn = 5, UART1_IRQn = 6, UART2_IRQn = 7, UART3_IRQn = 8,   PWM1_IRQn = 9, I2C0_IRQn = 10, I2C1_IRQn = 11, I2C2_IRQn = 12,   SPI_IRQn = 13, SSP0_IRQn = 14, SSP1_IRQn = 15, PLL0_IRQn = 16,   RTC_IRQn = 17, EINT0_IRQn = 18, EINT1_IRQn = 19, EINT2_IRQn = 20,   EINT3_IRQn = 21, ADC_IRQn = 22, BOD_IRQn = 23, USB_IRQn = 24,   CAN_IRQn = 25, DMA_IRQn = 26, I2S_IRQn = 27, ENET_IRQn = 28,   RIT_IRQn = 29, MCPWM_IRQn = 30, QEI_IRQn = 31, PLL1_IRQn = 32,   NonMaskableInt_IRQn = -14, HardFault_IRQn = -13, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,   UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,   SysTick_IRQn = -1, WDT_IRQn = 0, TIMER0_IRQn = 1, TIMER1_IRQn = 2,   TIMER2_IRQn = 3, TIMER3_IRQn = 4, UART0_IRQn = 5, UART1_IRQn = 6,   UART2_IRQn = 7, UART3_IRQn = 8, PWM1_IRQn = 9, I2C0_IRQn = 10,   I2C1_IRQn = 11, I2C2_IRQn = 12, Reserved0_IRQn = 13, SSP0_IRQn = 14,   SSP1_IRQn = 15, PLL0_IRQn = 16, RTC_IRQn = 17, EINT0_IRQn = 18,   EINT1_IRQn = 19, EINT2_IRQn = 20, EINT3_IRQn = 21, ADC_IRQn = 22,   BOD_IRQn = 23, USB_IRQn = 24, CAN_IRQn = 25, DMA_IRQn = 26,   I2S_IRQn = 27, ENET_IRQn = 28, MCI_IRQn = 29, MCPWM_IRQn = 30,   QEI_IRQn = 31, PLL1_IRQn = 32, USBActivity_IRQn = 33, CANActivity_IRQn = 34,   UART4_IRQn = 35, SSP2_IRQn = 36, LCD_IRQn = 37, GPIO_IRQn = 38,   PWM0_IRQn = 39, EEPROM_IRQn = 40, NonMaskableInt_IRQn = -14, HardFault_IRQn = -13,   MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5,   DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1, WWDG_IRQn = 0,   PVD_IRQn = 1, TAMPER_IRQn = 2, RTC_IRQn = 3, FLASH_IRQn = 4,   RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7, EXTI2_IRQn = 8,   EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Channel1_IRQn = 11, DMA1_Channel2_IRQn = 12,   DMA1_Channel3_IRQn = 13, DMA1_Channel4_IRQn = 14, DMA1_Channel5_IRQn = 15, DMA1_Channel6_IRQn = 16,   DMA1_Channel7_IRQn = 17, NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11,   UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2,   SysTick_IRQn = -1, WWDG_IRQn = 0, PVD_IRQn = 1, TAMP_STAMP_IRQn = 2,   RTC_WKUP_IRQn = 3, FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6,   EXTI1_IRQn = 7, EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10,   DMA1_Stream0_IRQn = 11, DMA1_Stream1_IRQn = 12, DMA1_Stream2_IRQn = 13, DMA1_Stream3_IRQn = 14,   DMA1_Stream4_IRQn = 15, DMA1_Stream5_IRQn = 16, DMA1_Stream6_IRQn = 17, ADC_IRQn = 18,   CAN1_TX_IRQn = 19, CAN1_RX0_IRQn = 20, CAN1_RX1_IRQn = 21, CAN1_SCE_IRQn = 22,   EXTI9_5_IRQn = 23, TIM1_BRK_TIM9_IRQn = 24, TIM1_UP_TIM10_IRQn = 25, TIM1_TRG_COM_TIM11_IRQn = 26,   TIM1_CC_IRQn = 27, TIM2_IRQn = 28, TIM3_IRQn = 29, TIM4_IRQn = 30,   I2C1_EV_IRQn = 31, I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33, I2C2_ER_IRQn = 34,   SPI1_IRQn = 35, SPI2_IRQn = 36, USART1_IRQn = 37, USART2_IRQn = 38,   USART3_IRQn = 39, EXTI15_10_IRQn = 40, RTC_Alarm_IRQn = 41, OTG_FS_WKUP_IRQn = 42,   TIM8_BRK_TIM12_IRQn = 43, TIM8_UP_TIM13_IRQn = 44, TIM8_TRG_COM_TIM14_IRQn = 45, TIM8_CC_IRQn = 46,   DMA1_Stream7_IRQn = 47, FSMC_IRQn = 48, SDIO_IRQn = 49, TIM5_IRQn = 50,   SPI3_IRQn = 51, UART4_IRQn = 52, UART5_IRQn = 53, TIM6_DAC_IRQn = 54,   TIM7_IRQn = 55, DMA2_Stream0_IRQn = 56, DMA2_Stream1_IRQn = 57, DMA2_Stream2_IRQn = 58,   DMA2_Stream3_IRQn = 59, DMA2_Stream4_IRQn = 60, ETH_IRQn = 61, ETH_WKUP_IRQn = 62,   CAN2_TX_IRQn = 63, CAN2_RX0_IRQn = 64, CAN2_RX1_IRQn = 65, CAN2_SCE_IRQn = 66,   OTG_FS_IRQn = 67, DMA2_Stream5_IRQn = 68, DMA2_Stream6_IRQn = 69, DMA2_Stream7_IRQn = 70,   USART6_IRQn = 71, I2C3_EV_IRQn = 72, I2C3_ER_IRQn = 73, OTG_HS_EP1_OUT_IRQn = 74,   OTG_HS_EP1_IN_IRQn = 75, OTG_HS_WKUP_IRQn = 76, OTG_HS_IRQn = 77, DCMI_IRQn = 78,   CRYP_IRQn = 79, HASH_RNG_IRQn = 80, NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12,   BusFault_IRQn = -11, UsageFault_IRQn = -10, SVCall_IRQn = -5, DebugMonitor_IRQn = -4,   PendSV_IRQn = -2, SysTick_IRQn = -1, WWDG_IRQn = 0, PVD_IRQn = 1,   TAMP_STAMP_IRQn = 2, RTC_WKUP_IRQn = 3, FLASH_IRQn = 4, RCC_IRQn = 5,   EXTI0_IRQn = 6, EXTI1_IRQn = 7, EXTI2_IRQn = 8, EXTI3_IRQn = 9,   EXTI4_IRQn = 10, DMA1_Stream0_IRQn = 11, DMA1_Stream1_IRQn = 12, DMA1_Stream2_IRQn = 13,   DMA1_Stream3_IRQn = 14, DMA1_Stream4_IRQn = 15, DMA1_Stream5_IRQn = 16, DMA1_Stream6_IRQn = 17,   ADC_IRQn = 18, CAN1_TX_IRQn = 19, CAN1_RX0_IRQn = 20, CAN1_RX1_IRQn = 21,   CAN1_SCE_IRQn = 22, EXTI9_5_IRQn = 23, TIM1_BRK_TIM9_IRQn = 24, TIM1_UP_TIM10_IRQn = 25,   TIM1_TRG_COM_TIM11_IRQn = 26, TIM1_CC_IRQn = 27, TIM2_IRQn = 28, TIM3_IRQn = 29,   TIM4_IRQn = 30, I2C1_EV_IRQn = 31, I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33,   I2C2_ER_IRQn = 34, SPI1_IRQn = 35, SPI2_IRQn = 36, USART1_IRQn = 37,   USART2_IRQn = 38, USART3_IRQn = 39, EXTI15_10_IRQn = 40, RTC_Alarm_IRQn = 41,   OTG_FS_WKUP_IRQn = 42, TIM8_BRK_TIM12_IRQn = 43, TIM8_UP_TIM13_IRQn = 44, TIM8_TRG_COM_TIM14_IRQn = 45,   TIM8_CC_IRQn = 46, DMA1_Stream7_IRQn = 47, FSMC_IRQn = 48, SDIO_IRQn = 49,   TIM5_IRQn = 50, SPI3_IRQn = 51, UART4_IRQn = 52, UART5_IRQn = 53,   TIM6_DAC_IRQn = 54, TIM7_IRQn = 55, DMA2_Stream0_IRQn = 56, DMA2_Stream1_IRQn = 57,   DMA2_Stream2_IRQn = 58, DMA2_Stream3_IRQn = 59, DMA2_Stream4_IRQn = 60, ETH_IRQn = 61,   ETH_WKUP_IRQn = 62, CAN2_TX_IRQn = 63, CAN2_RX0_IRQn = 64, CAN2_RX1_IRQn = 65,   CAN2_SCE_IRQn = 66, OTG_FS_IRQn = 67, DMA2_Stream5_IRQn = 68, DMA2_Stream6_IRQn = 69,   DMA2_Stream7_IRQn = 70, USART6_IRQn = 71, I2C3_EV_IRQn = 72, I2C3_ER_IRQn = 73,   OTG_HS_EP1_OUT_IRQn = 74, OTG_HS_EP1_IN_IRQn = 75, OTG_HS_WKUP_IRQn = 76, OTG_HS_IRQn = 77,   DCMI_IRQn = 78, CRYP_IRQn = 79, HASH_RNG_IRQn = 80, FPU_IRQn = 81,   NonMaskableInt_IRQn = -14, MemoryManagement_IRQn = -12, BusFault_IRQn = -11, UsageFault_IRQn = -10,   SVC_IRQn = -5, DebugMonitor_IRQn = -4, PendSV_IRQn = -2, SysTick_IRQn = -1,   WWDG_IRQn = 0, PVD_IRQn = 1, TAMPER_STAMP_IRQn = 2, RTC_WKUP_IRQn = 3,   FLASH_IRQn = 4, RCC_IRQn = 5, EXTI0_IRQn = 6, EXTI1_IRQn = 7,   EXTI2_IRQn = 8, EXTI3_IRQn = 9, EXTI4_IRQn = 10, DMA1_Channel1_IRQn = 11,   DMA1_Channel2_IRQn = 12, DMA1_Channel3_IRQn = 13, DMA1_Channel4_IRQn = 14, DMA1_Channel5_IRQn = 15,   DMA1_Channel6_IRQn = 16, DMA1_Channel7_IRQn = 17, ADC1_IRQn = 18, USB_HP_IRQn = 19,   USB_LP_IRQn = 20, DAC_IRQn = 21, COMP_IRQn = 22, EXTI9_5_IRQn = 23,   LCD_IRQn = 24, TIM9_IRQn = 25, TIM10_IRQn = 26, TIM11_IRQn = 27,   TIM2_IRQn = 28, TIM3_IRQn = 29, TIM4_IRQn = 30, I2C1_EV_IRQn = 31,   I2C1_ER_IRQn = 32, I2C2_EV_IRQn = 33, I2C2_ER_IRQn = 34, SPI1_IRQn = 35,   SPI2_IRQn = 36, USART1_IRQn = 37, USART2_IRQn = 38, USART3_IRQn = 39,   EXTI15_10_IRQn = 40, RTC_Alarm_IRQn = 41, USB_FS_WKUP_IRQn = 42, TIM6_IRQn = 43,   TIM7_IRQn = 44, SDIO_IRQn = 45, TIM5_IRQn = 46, SPI3_IRQn = 47,   UART4_IRQn = 48, UART5_IRQn = 49, DMA2_Channel1_IRQn = 50, DMA2_Channel2_IRQn = 51,   DMA2_Channel3_IRQn = 52, DMA2_Channel4_IRQn = 53, DMA2_Channel5_IRQn = 54, AES_IRQn = 55,   COMP_ACQ_IRQn = 56 }

---

Detailed Description

Cortex-M3 Core Peripheral Access Layer Header File for NXP LPC177x_8x Series.

Version:

1.0

Date:

02. June. 2011

Author:

NXP MCU SW Application Team

Copyright(C) 2011, NXP Semiconductor All rights reserved.

Software that is described herein is for illustrative purposes only which provides customers with programming information regarding the products. This software is supplied "AS IS" without any warranties. NXP Semiconductors assumes no responsibility or liability for the use of the software, conveys no license or title under any patent, copyright, or mask work right to the product. NXP Semiconductors reserves the right to make changes in the software without notification. NXP Semiconductors also make no representation or warranty that such application will be suitable for the specified use without further testing or modification. Permission to use, copy, modify, and distribute this software and its documentation is hereby granted, under NXP Semiconductors' relevant copyright in the software, without fee, provided that it is used in conjunction with NXP Semiconductors microcontrollers. This copyright, permission, and disclaimer notice must appear in all copies of this code.

---

Define Documentation

#define __MPU_PRESENT   1

MPU present or not

#define __NVIC_PRIO_BITS   5

Number of Bits used for Priority Levels

#define __Vendor_SysTickConfig   0

Set to 1 if different SysTick Config is used

#define LPC_FLASH_BASE   (0x00000000UL)

#define LPC_RAM_BASE   (0x10000000UL)

#define LPC_PERI_RAM_BASE   (0x20000000UL)

#define LPC_APB0_BASE   (0x40000000UL)

#define LPC_APB1_BASE   (0x40080000UL)

#define LPC_AHBRAM1_BASE   (0x20004000UL)

#define LPC_AHB_BASE   (0x20080000UL)

#define LPC_CM3_BASE   (0xE0000000UL)

#define LPC_WDT_BASE   (LPC_APB0_BASE + 0x00000)

#define LPC_TIM0_BASE   (LPC_APB0_BASE + 0x04000)

#define LPC_TIM1_BASE   (LPC_APB0_BASE + 0x08000)

#define LPC_UART0_BASE   (LPC_APB0_BASE + 0x0C000)

#define LPC_UART1_BASE   (LPC_APB0_BASE + 0x10000)

#define LPC_PWM0_BASE   (LPC_APB0_BASE + 0x14000)

#define LPC_PWM1_BASE   (LPC_APB0_BASE + 0x18000)

#define LPC_I2C0_BASE   (LPC_APB0_BASE + 0x1C000)

#define LPC_RTC_BASE   (LPC_APB0_BASE + 0x24000)

#define LPC_GPIOINT_BASE   (LPC_APB0_BASE + 0x28080)

#define LPC_IOCON_BASE   (LPC_APB0_BASE + 0x2C000)

Referenced by GpioPinConfigGet(), GpioPinConfigSet(), and GpioPortConfigSet().

#define LPC_SSP1_BASE   (LPC_APB0_BASE + 0x30000)

#define LPC_ADC_BASE   (LPC_APB0_BASE + 0x34000)

#define LPC_CANAF_RAM_BASE   (LPC_APB0_BASE + 0x38000)

#define LPC_CANAF_BASE   (LPC_APB0_BASE + 0x3C000)

#define LPC_CANCR_BASE   (LPC_APB0_BASE + 0x40000)

#define LPC_CAN1_BASE   (LPC_APB0_BASE + 0x44000)

#define LPC_CAN2_BASE   (LPC_APB0_BASE + 0x48000)

#define LPC_I2C1_BASE   (LPC_APB0_BASE + 0x5C000)

#define LPC_SSP0_BASE   (LPC_APB1_BASE + 0x08000)

#define LPC_DAC_BASE   (LPC_APB1_BASE + 0x0C000)

#define LPC_TIM2_BASE   (LPC_APB1_BASE + 0x10000)

#define LPC_TIM3_BASE   (LPC_APB1_BASE + 0x14000)

#define LPC_UART2_BASE   (LPC_APB1_BASE + 0x18000)

#define LPC_UART3_BASE   (LPC_APB1_BASE + 0x1C000)

#define LPC_I2C2_BASE   (LPC_APB1_BASE + 0x20000)

#define LPC_UART4_BASE   (LPC_APB1_BASE + 0x24000)

#define LPC_I2S_BASE   (LPC_APB1_BASE + 0x28000)

#define LPC_SSP2_BASE   (LPC_APB1_BASE + 0x2C000)

#define LPC_MCPWM_BASE   (LPC_APB1_BASE + 0x38000)

#define LPC_QEI_BASE   (LPC_APB1_BASE + 0x3C000)

#define LPC_MCI_BASE   (LPC_APB1_BASE + 0x40000)

#define LPC_SC_BASE   (LPC_APB1_BASE + 0x7C000)

#define LPC_GPDMA_BASE   (LPC_AHB_BASE + 0x00000)

#define LPC_GPDMACH0_BASE   (LPC_AHB_BASE + 0x00100)

#define LPC_GPDMACH1_BASE   (LPC_AHB_BASE + 0x00120)

#define LPC_GPDMACH2_BASE   (LPC_AHB_BASE + 0x00140)

#define LPC_GPDMACH3_BASE   (LPC_AHB_BASE + 0x00160)

#define LPC_GPDMACH4_BASE   (LPC_AHB_BASE + 0x00180)

#define LPC_GPDMACH5_BASE   (LPC_AHB_BASE + 0x001A0)

#define LPC_GPDMACH6_BASE   (LPC_AHB_BASE + 0x001C0)

#define LPC_GPDMACH7_BASE   (LPC_AHB_BASE + 0x001E0)

#define LPC_EMAC_BASE   (LPC_AHB_BASE + 0x04000)

#define LPC_LCD_BASE   (LPC_AHB_BASE + 0x08000)

#define LPC_USB_BASE   (LPC_AHB_BASE + 0x0C000)

#define LPC_CRC_BASE   (LPC_AHB_BASE + 0x10000)

#define LPC_GPIO0_BASE   (LPC_AHB_BASE + 0x18000)

#define LPC_GPIO1_BASE   (LPC_AHB_BASE + 0x18020)

#define LPC_GPIO2_BASE   (LPC_AHB_BASE + 0x18040)

#define LPC_GPIO3_BASE   (LPC_AHB_BASE + 0x18060)

#define LPC_GPIO4_BASE   (LPC_AHB_BASE + 0x18080)

#define LPC_GPIO5_BASE   (LPC_AHB_BASE + 0x180A0)

#define LPC_EMC_BASE   (LPC_AHB_BASE + 0x1C000)

#define LPC_EEPROM_BASE   (LPC_FLASH_BASE+ 0x200080)

#define LPC_SC   ((LPC_SC_TypeDef *) LPC_SC_BASE )

#define LPC_WDT   ((LPC_WDT_TypeDef *) LPC_WDT_BASE )

#define LPC_TIM0   ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )

#define LPC_TIM1   ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )

#define LPC_TIM2   ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )

#define LPC_TIM3   ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )

#define LPC_UART0   ((LPC_UART_TypeDef *) LPC_UART0_BASE )

#define LPC_UART1   ((LPC_UART1_TypeDef *) LPC_UART1_BASE )

#define LPC_UART2   ((LPC_UART_TypeDef *) LPC_UART2_BASE )

#define LPC_UART3   ((LPC_UART_TypeDef *) LPC_UART3_BASE )

#define LPC_UART4   ((LPC_UART4_TypeDef *) LPC_UART4_BASE )

#define LPC_PWM0   ((LPC_PWM_TypeDef *) LPC_PWM0_BASE )

#define LPC_PWM1   ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )

#define LPC_I2C0   ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )

#define LPC_I2C1   ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )

#define LPC_I2C2   ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )

#define LPC_I2S   ((LPC_I2S_TypeDef *) LPC_I2S_BASE )

#define LPC_RTC   ((LPC_RTC_TypeDef *) LPC_RTC_BASE )

#define LPC_GPIOINT   ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )

#define LPC_IOCON   ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )

#define LPC_SSP0   ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )

#define LPC_SSP1   ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )

#define LPC_SSP2   ((LPC_SSP_TypeDef *) LPC_SSP2_BASE )

#define LPC_ADC   ((LPC_ADC_TypeDef *) LPC_ADC_BASE )

#define LPC_DAC   ((LPC_DAC_TypeDef *) LPC_DAC_BASE )

#define LPC_CANAF_RAM   ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)

#define LPC_CANAF   ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )

#define LPC_CANCR   ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )

#define LPC_CAN1   ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )

#define LPC_CAN2   ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )

#define LPC_MCPWM   ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )

#define LPC_QEI   ((LPC_QEI_TypeDef *) LPC_QEI_BASE )

#define LPC_MCI   ((LPC_MCI_TypeDef *) LPC_MCI_BASE )

Referenced by Lpc177x_8x_MciCmd_ReadBlock(), Lpc177x_8x_MciCmd_SelectCard(), Lpc177x_8x_MciCmd_StopTransmission(), Lpc177x_8x_MciCmd_WriteBlock(), Lpc177x_8x_MciCmdProcess(), Lpc177x_8x_MciDATA_END_InterruptService(), Lpc177x_8x_MciDataErrorProcess(), Lpc177x_8x_MciFIFOInterruptService(), Lpc177x_8x_MciGetCardStatus(), Lpc177x_8x_MciGetCmdResp(), Lpc177x_8x_MciGetCSD(), Lpc177x_8x_MciInit(), Lpc177x_8x_MciPowerOff(), Lpc177x_8x_MciReadBlock(), Lpc177x_8x_MciRXDisable(), Lpc177x_8x_MciRXEnable(), Lpc177x_8x_MciSendCmd(), Lpc177x_8x_MciSet_MCIClock(), Lpc177x_8x_MciSetBlockLen(), Lpc177x_8x_MciSetBusWidth(), Lpc177x_8x_MciSetOutputMode(), Lpc177x_8x_MciTXDisable(), Lpc177x_8x_MciTXEnable(), and Lpc177x_8x_MciWriteBlock().

#define LPC_GPDMA   ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )

#define LPC_GPDMACH0   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )

#define LPC_GPDMACH1   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )

#define LPC_GPDMACH2   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )

#define LPC_GPDMACH3   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )

#define LPC_GPDMACH4   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )

#define LPC_GPDMACH5   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )

#define LPC_GPDMACH6   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )

#define LPC_GPDMACH7   ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )

#define LPC_EMAC   ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )

#define LPC_LCD   ((LPC_LCD_TypeDef *) LPC_LCD_BASE )

#define LPC_USB   ((LPC_USB_TypeDef *) LPC_USB_BASE )

#define LPC_GPIO0   ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )

#define LPC_GPIO1   ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )

#define LPC_GPIO2   ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )

#define LPC_GPIO3   ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )

#define LPC_GPIO4   ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )

#define LPC_GPIO5   ((LPC_GPIO_TypeDef *) LPC_GPIO5_BASE )

#define LPC_EMC   ((LPC_EMC_TypeDef *) LPC_EMC_BASE )

Referenced by Lpc177x_8x_EmcConfigEndianMode(), Lpc177x_8x_EmcDynCtrlClockControl(), Lpc177x_8x_EmcDynCtrlClockEnable(), Lpc177x_8x_EmcDynCtrlMMC(), Lpc177x_8x_EmcDynCtrlPowerDownMode(), Lpc177x_8x_EmcDynCtrlSDRAMCmd(), Lpc177x_8x_EmcDynCtrlSelfRefresh(), Lpc177x_8x_EmcDynMemCAS(), Lpc177x_8x_EmcDynMemConfigAM(), Lpc177x_8x_EmcDynMemConfigB(), Lpc177x_8x_EmcDynMemConfigMD(), Lpc177x_8x_EmcDynMemConfigP(), Lpc177x_8x_EmcDynMemRAS(), Lpc177x_8x_EmcInit(), Lpc177x_8x_EmcSDRAMInit(), Lpc177x_8x_EmcSetDynMemoryParameter(), Lpc177x_8x_EmcSetStaticMemoryParameter(), Lpc177x_8x_EmcStaticExtendedWait(), Lpc177x_8x_EmcStaticMemConfigB(), Lpc177x_8x_EmcStaticMemConfigEW(), Lpc177x_8x_EmcStaticMemConfigMW(), Lpc177x_8x_EmcStaticMemConfigPB(), Lpc177x_8x_EmcStaticMemConfigPC(), Lpc177x_8x_EmcStaticMemConfigPM(), and Lpc177x_8x_EmcStaticMemConfigpP().

#define LPC_CRC   ((LPC_CRC_TypeDef *) LPC_CRC_BASE )

#define LPC_EEPROM   ((LPC_EEPROM_TypeDef *) LPC_EEPROM_BASE )

Referenced by Lpc177x_8x_EepromInit(), Lpc177x_8x_EepromRead(), and Lpc177x_8x_EepromWrite().

---

Typedef Documentation

typedef enum IRQn IRQn_Type

---

Enumeration Type Documentation

enum IRQn

Enumerator:

NonMaskableInt_IRQn	2 Non Maskable Interrupt
MemoryManagement_IRQn	4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M3 System Tick Interrupt
IROn_SUPC
IROn_RSTC
IROn_RTC
IROn_RTT
IROn_WDG
IROn_PMC
IROn_EFC0
IROn_EFC1
IROn_DBGU
IROn_HSMC4
IROn_PIOA
IROn_PIOB
IROn_PIOC
IROn_US0
IROn_US1
IROn_US2
IROn_US3
IROn_MCI0
IROn_TWI0
IROn_TWI1
IROn_SPI0
IROn_SSC0
IROn_TC0
IROn_TC1
IROn_TC2
IROn_PWMC
IROn_ADCC0
IROn_ADCC1
IROn_HDMA
IROn_UDPHS
NonMaskableInt_IRQn	2 Non Maskable Interrupt
HardFault_IRQn	3 Cortex-M3 Hard Fault Interrupt
MemoryManagement_IRQn	4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M3 System Tick Interrupt
WDT_IRQn	Watchdog Timer Interrupt
TIMER0_IRQn	Timer0 Interrupt
TIMER1_IRQn	Timer1 Interrupt
TIMER2_IRQn	Timer2 Interrupt
TIMER3_IRQn	Timer3 Interrupt
UART0_IRQn	UART0 Interrupt
UART1_IRQn	UART1 Interrupt
UART2_IRQn	UART2 Interrupt
UART3_IRQn	UART3 Interrupt
PWM1_IRQn	PWM1 Interrupt
I2C0_IRQn	I2C0 Interrupt
I2C1_IRQn	I2C1 Interrupt
I2C2_IRQn	I2C2 Interrupt
SPI_IRQn	SPI Interrupt
SSP0_IRQn	SSP0 Interrupt
SSP1_IRQn	SSP1 Interrupt
PLL0_IRQn	PLL0 Lock (Main PLL) Interrupt
RTC_IRQn	Real Time Clock Interrupt
EINT0_IRQn	External Interrupt 0 Interrupt
EINT1_IRQn	External Interrupt 1 Interrupt
EINT2_IRQn	External Interrupt 2 Interrupt
EINT3_IRQn	External Interrupt 3 Interrupt
ADC_IRQn	A/D Converter Interrupt
BOD_IRQn	Brown-Out Detect Interrupt
USB_IRQn	USB Interrupt
CAN_IRQn	CAN Interrupt
DMA_IRQn	General Purpose DMA Interrupt
I2S_IRQn	I2S Interrupt
ENET_IRQn	Ethernet Interrupt
RIT_IRQn	Repetitive Interrupt Timer Interrupt
MCPWM_IRQn	Motor Control PWM Interrupt
QEI_IRQn	Quadrature Encoder Interface Interrupt
PLL1_IRQn	PLL1 Lock (USB PLL) Interrupt
NonMaskableInt_IRQn	2 Non Maskable Interrupt
HardFault_IRQn	3 Cortex-M3 Hard Fault Interrupt
MemoryManagement_IRQn	4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M3 System Tick Interrupt
WDT_IRQn	Watchdog Timer Interrupt
TIMER0_IRQn	Timer0 Interrupt
TIMER1_IRQn	Timer1 Interrupt
TIMER2_IRQn	Timer2 Interrupt
TIMER3_IRQn	Timer3 Interrupt
UART0_IRQn	UART0 Interrupt
UART1_IRQn	UART1 Interrupt
UART2_IRQn	UART2 Interrupt
UART3_IRQn	UART3 Interrupt
PWM1_IRQn	PWM1 Interrupt
I2C0_IRQn	I2C0 Interrupt
I2C1_IRQn	I2C1 Interrupt
I2C2_IRQn	I2C2 Interrupt
Reserved0_IRQn	Reserved
SSP0_IRQn	SSP0 Interrupt
SSP1_IRQn	SSP1 Interrupt
PLL0_IRQn	PLL0 Lock (Main PLL) Interrupt
RTC_IRQn	Real Time Clock Interrupt
EINT0_IRQn	External Interrupt 0 Interrupt
EINT1_IRQn	External Interrupt 1 Interrupt
EINT2_IRQn	External Interrupt 2 Interrupt
EINT3_IRQn	External Interrupt 3 Interrupt
ADC_IRQn	A/D Converter Interrupt
BOD_IRQn	Brown-Out Detect Interrupt
USB_IRQn	USB Interrupt
CAN_IRQn	CAN Interrupt
DMA_IRQn	General Purpose DMA Interrupt
I2S_IRQn	I2S Interrupt
ENET_IRQn	Ethernet Interrupt
MCI_IRQn	SD/MMC card I/F Interrupt
MCPWM_IRQn	Motor Control PWM Interrupt
QEI_IRQn	Quadrature Encoder Interface Interrupt
PLL1_IRQn	PLL1 Lock (USB PLL) Interrupt
USBActivity_IRQn	USB Activity interrupt
CANActivity_IRQn	CAN Activity interrupt
UART4_IRQn	UART4 Interrupt
SSP2_IRQn	SSP2 Interrupt
LCD_IRQn	LCD Interrupt
GPIO_IRQn	GPIO Interrupt
PWM0_IRQn	PWM0 Interrupt
EEPROM_IRQn	EEPROM Interrupt
NonMaskableInt_IRQn	2 Non Maskable Interrupt
HardFault_IRQn	3 Cortex-M3 Hard Fault Interrupt
MemoryManagement_IRQn	4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M3 System Tick Interrupt
WWDG_IRQn	Window WatchDog Interrupt
PVD_IRQn	PVD through EXTI Line detection Interrupt
TAMPER_IRQn	Tamper Interrupt
RTC_IRQn	RTC global Interrupt
FLASH_IRQn	FLASH global Interrupt
RCC_IRQn	RCC global Interrupt
EXTI0_IRQn	EXTI Line0 Interrupt
EXTI1_IRQn	EXTI Line1 Interrupt
EXTI2_IRQn	EXTI Line2 Interrupt
EXTI3_IRQn	EXTI Line3 Interrupt
EXTI4_IRQn	EXTI Line4 Interrupt
DMA1_Channel1_IRQn	DMA1 Channel 1 global Interrupt
DMA1_Channel2_IRQn	DMA1 Channel 2 global Interrupt
DMA1_Channel3_IRQn	DMA1 Channel 3 global Interrupt
DMA1_Channel4_IRQn	DMA1 Channel 4 global Interrupt
DMA1_Channel5_IRQn	DMA1 Channel 5 global Interrupt
DMA1_Channel6_IRQn	DMA1 Channel 6 global Interrupt
DMA1_Channel7_IRQn	DMA1 Channel 7 global Interrupt
NonMaskableInt_IRQn	2 Non Maskable Interrupt
MemoryManagement_IRQn	4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M3 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M3 System Tick Interrupt
WWDG_IRQn	Window WatchDog Interrupt
PVD_IRQn	PVD through EXTI Line detection Interrupt
TAMP_STAMP_IRQn	Tamper and TimeStamp interrupts through the EXTI line
RTC_WKUP_IRQn	RTC Wakeup interrupt through the EXTI line
FLASH_IRQn	FLASH global Interrupt
RCC_IRQn	RCC global Interrupt
EXTI0_IRQn	EXTI Line0 Interrupt
EXTI1_IRQn	EXTI Line1 Interrupt
EXTI2_IRQn	EXTI Line2 Interrupt
EXTI3_IRQn	EXTI Line3 Interrupt
EXTI4_IRQn	EXTI Line4 Interrupt
DMA1_Stream0_IRQn	DMA1 Stream 0 global Interrupt
DMA1_Stream1_IRQn	DMA1 Stream 1 global Interrupt
DMA1_Stream2_IRQn	DMA1 Stream 2 global Interrupt
DMA1_Stream3_IRQn	DMA1 Stream 3 global Interrupt
DMA1_Stream4_IRQn	DMA1 Stream 4 global Interrupt
DMA1_Stream5_IRQn	DMA1 Stream 5 global Interrupt
DMA1_Stream6_IRQn	DMA1 Stream 6 global Interrupt
ADC_IRQn	ADC1, ADC2 and ADC3 global Interrupts
CAN1_TX_IRQn	CAN1 TX Interrupt
CAN1_RX0_IRQn	CAN1 RX0 Interrupt
CAN1_RX1_IRQn	CAN1 RX1 Interrupt
CAN1_SCE_IRQn	CAN1 SCE Interrupt
EXTI9_5_IRQn	External Line[9:5] Interrupts
TIM1_BRK_TIM9_IRQn	TIM1 Break interrupt and TIM9 global interrupt
TIM1_UP_TIM10_IRQn	TIM1 Update Interrupt and TIM10 global interrupt
TIM1_TRG_COM_TIM11_IRQn	TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt
TIM1_CC_IRQn	TIM1 Capture Compare Interrupt
TIM2_IRQn	TIM2 global Interrupt
TIM3_IRQn	TIM3 global Interrupt
TIM4_IRQn	TIM4 global Interrupt
I2C1_EV_IRQn	I2C1 Event Interrupt
I2C1_ER_IRQn	I2C1 Error Interrupt
I2C2_EV_IRQn	I2C2 Event Interrupt
I2C2_ER_IRQn	I2C2 Error Interrupt
SPI1_IRQn	SPI1 global Interrupt
SPI2_IRQn	SPI2 global Interrupt
USART1_IRQn	USART1 global Interrupt
USART2_IRQn	USART2 global Interrupt
USART3_IRQn	USART3 global Interrupt
EXTI15_10_IRQn	External Line[15:10] Interrupts
RTC_Alarm_IRQn	RTC Alarm (A and B) through EXTI Line Interrupt
OTG_FS_WKUP_IRQn	USB OTG FS Wakeup through EXTI line interrupt
TIM8_BRK_TIM12_IRQn	TIM8 Break Interrupt and TIM12 global interrupt
TIM8_UP_TIM13_IRQn	TIM8 Update Interrupt and TIM13 global interrupt
TIM8_TRG_COM_TIM14_IRQn	TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
TIM8_CC_IRQn	TIM8 Capture Compare Interrupt
DMA1_Stream7_IRQn	DMA1 Stream7 Interrupt
FSMC_IRQn	FSMC global Interrupt
SDIO_IRQn	SDIO global Interrupt
TIM5_IRQn	TIM5 global Interrupt
SPI3_IRQn	SPI3 global Interrupt
UART4_IRQn	UART4 global Interrupt
UART5_IRQn	UART5 global Interrupt
TIM6_DAC_IRQn	TIM6 global and DAC1&2 underrun error interrupts
TIM7_IRQn	TIM7 global interrupt
DMA2_Stream0_IRQn	DMA2 Stream 0 global Interrupt
DMA2_Stream1_IRQn	DMA2 Stream 1 global Interrupt
DMA2_Stream2_IRQn	DMA2 Stream 2 global Interrupt
DMA2_Stream3_IRQn	DMA2 Stream 3 global Interrupt
DMA2_Stream4_IRQn	DMA2 Stream 4 global Interrupt
ETH_IRQn	Ethernet global Interrupt
ETH_WKUP_IRQn	Ethernet Wakeup through EXTI line Interrupt
CAN2_TX_IRQn	CAN2 TX Interrupt
CAN2_RX0_IRQn	CAN2 RX0 Interrupt
CAN2_RX1_IRQn	CAN2 RX1 Interrupt
CAN2_SCE_IRQn	CAN2 SCE Interrupt
OTG_FS_IRQn	USB OTG FS global Interrupt
DMA2_Stream5_IRQn	DMA2 Stream 5 global interrupt
DMA2_Stream6_IRQn	DMA2 Stream 6 global interrupt
DMA2_Stream7_IRQn	DMA2 Stream 7 global interrupt
USART6_IRQn	USART6 global interrupt
I2C3_EV_IRQn	I2C3 event interrupt
I2C3_ER_IRQn	I2C3 error interrupt
OTG_HS_EP1_OUT_IRQn	USB OTG HS End Point 1 Out global interrupt
OTG_HS_EP1_IN_IRQn	USB OTG HS End Point 1 In global interrupt
OTG_HS_WKUP_IRQn	USB OTG HS Wakeup through EXTI interrupt
OTG_HS_IRQn	USB OTG HS global interrupt
DCMI_IRQn	DCMI global interrupt
CRYP_IRQn	CRYP crypto global interrupt
HASH_RNG_IRQn	Hash and Rng global interrupt
NonMaskableInt_IRQn	2 Non Maskable Interrupt
MemoryManagement_IRQn	4 Cortex-M4 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M4 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M4 Usage Fault Interrupt
SVCall_IRQn	11 Cortex-M4 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M4 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M4 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M4 System Tick Interrupt
WWDG_IRQn	Window WatchDog Interrupt
PVD_IRQn	PVD through EXTI Line detection Interrupt
TAMP_STAMP_IRQn	Tamper and TimeStamp interrupts through the EXTI line
RTC_WKUP_IRQn	RTC Wakeup interrupt through the EXTI line
FLASH_IRQn	FLASH global Interrupt
RCC_IRQn	RCC global Interrupt
EXTI0_IRQn	EXTI Line0 Interrupt
EXTI1_IRQn	EXTI Line1 Interrupt
EXTI2_IRQn	EXTI Line2 Interrupt
EXTI3_IRQn	EXTI Line3 Interrupt
EXTI4_IRQn	EXTI Line4 Interrupt
DMA1_Stream0_IRQn	DMA1 Stream 0 global Interrupt
DMA1_Stream1_IRQn	DMA1 Stream 1 global Interrupt
DMA1_Stream2_IRQn	DMA1 Stream 2 global Interrupt
DMA1_Stream3_IRQn	DMA1 Stream 3 global Interrupt
DMA1_Stream4_IRQn	DMA1 Stream 4 global Interrupt
DMA1_Stream5_IRQn	DMA1 Stream 5 global Interrupt
DMA1_Stream6_IRQn	DMA1 Stream 6 global Interrupt
ADC_IRQn	ADC1, ADC2 and ADC3 global Interrupts
CAN1_TX_IRQn	CAN1 TX Interrupt
CAN1_RX0_IRQn	CAN1 RX0 Interrupt
CAN1_RX1_IRQn	CAN1 RX1 Interrupt
CAN1_SCE_IRQn	CAN1 SCE Interrupt
EXTI9_5_IRQn	External Line[9:5] Interrupts
TIM1_BRK_TIM9_IRQn	TIM1 Break interrupt and TIM9 global interrupt
TIM1_UP_TIM10_IRQn	TIM1 Update Interrupt and TIM10 global interrupt
TIM1_TRG_COM_TIM11_IRQn	TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt
TIM1_CC_IRQn	TIM1 Capture Compare Interrupt
TIM2_IRQn	TIM2 global Interrupt
TIM3_IRQn	TIM3 global Interrupt
TIM4_IRQn	TIM4 global Interrupt
I2C1_EV_IRQn	I2C1 Event Interrupt
I2C1_ER_IRQn	I2C1 Error Interrupt
I2C2_EV_IRQn	I2C2 Event Interrupt
I2C2_ER_IRQn	I2C2 Error Interrupt
SPI1_IRQn	SPI1 global Interrupt
SPI2_IRQn	SPI2 global Interrupt
USART1_IRQn	USART1 global Interrupt
USART2_IRQn	USART2 global Interrupt
USART3_IRQn	USART3 global Interrupt
EXTI15_10_IRQn	External Line[15:10] Interrupts
RTC_Alarm_IRQn	RTC Alarm (A and B) through EXTI Line Interrupt
OTG_FS_WKUP_IRQn	USB OTG FS Wakeup through EXTI line interrupt
TIM8_BRK_TIM12_IRQn	TIM8 Break Interrupt and TIM12 global interrupt
TIM8_UP_TIM13_IRQn	TIM8 Update Interrupt and TIM13 global interrupt
TIM8_TRG_COM_TIM14_IRQn	TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt
TIM8_CC_IRQn	TIM8 Capture Compare Interrupt
DMA1_Stream7_IRQn	DMA1 Stream7 Interrupt
FSMC_IRQn	FSMC global Interrupt
SDIO_IRQn	SDIO global Interrupt
TIM5_IRQn	TIM5 global Interrupt
SPI3_IRQn	SPI3 global Interrupt
UART4_IRQn	UART4 global Interrupt
UART5_IRQn	UART5 global Interrupt
TIM6_DAC_IRQn	TIM6 global and DAC1&2 underrun error interrupts
TIM7_IRQn	TIM7 global interrupt
DMA2_Stream0_IRQn	DMA2 Stream 0 global Interrupt
DMA2_Stream1_IRQn	DMA2 Stream 1 global Interrupt
DMA2_Stream2_IRQn	DMA2 Stream 2 global Interrupt
DMA2_Stream3_IRQn	DMA2 Stream 3 global Interrupt
DMA2_Stream4_IRQn	DMA2 Stream 4 global Interrupt
ETH_IRQn	Ethernet global Interrupt
ETH_WKUP_IRQn	Ethernet Wakeup through EXTI line Interrupt
CAN2_TX_IRQn	CAN2 TX Interrupt
CAN2_RX0_IRQn	CAN2 RX0 Interrupt
CAN2_RX1_IRQn	CAN2 RX1 Interrupt
CAN2_SCE_IRQn	CAN2 SCE Interrupt
OTG_FS_IRQn	USB OTG FS global Interrupt
DMA2_Stream5_IRQn	DMA2 Stream 5 global interrupt
DMA2_Stream6_IRQn	DMA2 Stream 6 global interrupt
DMA2_Stream7_IRQn	DMA2 Stream 7 global interrupt
USART6_IRQn	USART6 global interrupt
I2C3_EV_IRQn	I2C3 event interrupt
I2C3_ER_IRQn	I2C3 error interrupt
OTG_HS_EP1_OUT_IRQn	USB OTG HS End Point 1 Out global interrupt
OTG_HS_EP1_IN_IRQn	USB OTG HS End Point 1 In global interrupt
OTG_HS_WKUP_IRQn	USB OTG HS Wakeup through EXTI interrupt
OTG_HS_IRQn	USB OTG HS global interrupt
DCMI_IRQn	DCMI global interrupt
CRYP_IRQn	CRYP crypto global interrupt
HASH_RNG_IRQn	Hash and Rng global interrupt
FPU_IRQn	FPU global interrupt
NonMaskableInt_IRQn	2 Non Maskable Interrupt
MemoryManagement_IRQn	4 Cortex-M3 Memory Management Interrupt
BusFault_IRQn	5 Cortex-M3 Bus Fault Interrupt
UsageFault_IRQn	6 Cortex-M3 Usage Fault Interrupt
SVC_IRQn	11 Cortex-M3 SV Call Interrupt
DebugMonitor_IRQn	12 Cortex-M3 Debug Monitor Interrupt
PendSV_IRQn	14 Cortex-M3 Pend SV Interrupt
SysTick_IRQn	15 Cortex-M3 System Tick Interrupt
WWDG_IRQn	Window WatchDog Interrupt
PVD_IRQn	PVD through EXTI Line detection Interrupt
TAMPER_STAMP_IRQn	Tamper and Time Stamp through EXTI Line Interrupts
RTC_WKUP_IRQn	RTC Wakeup Timer through EXTI Line Interrupt
FLASH_IRQn	FLASH global Interrupt
RCC_IRQn	RCC global Interrupt
EXTI0_IRQn	EXTI Line0 Interrupt
EXTI1_IRQn	EXTI Line1 Interrupt
EXTI2_IRQn	EXTI Line2 Interrupt
EXTI3_IRQn	EXTI Line3 Interrupt
EXTI4_IRQn	EXTI Line4 Interrupt
DMA1_Channel1_IRQn	DMA1 Channel 1 global Interrupt
DMA1_Channel2_IRQn	DMA1 Channel 2 global Interrupt
DMA1_Channel3_IRQn	DMA1 Channel 3 global Interrupt
DMA1_Channel4_IRQn	DMA1 Channel 4 global Interrupt
DMA1_Channel5_IRQn	DMA1 Channel 5 global Interrupt
DMA1_Channel6_IRQn	DMA1 Channel 6 global Interrupt
DMA1_Channel7_IRQn	DMA1 Channel 7 global Interrupt
ADC1_IRQn	ADC1 global Interrupt
USB_HP_IRQn	USB High Priority Interrupt
USB_LP_IRQn	USB Low Priority Interrupt
DAC_IRQn	DAC Interrupt
COMP_IRQn	Comparator through EXTI Line Interrupt
EXTI9_5_IRQn	External Line[9:5] Interrupts
LCD_IRQn	LCD Interrupt
TIM9_IRQn	TIM9 global Interrupt
TIM10_IRQn	TIM10 global Interrupt
TIM11_IRQn	TIM11 global Interrupt
TIM2_IRQn	TIM2 global Interrupt
TIM3_IRQn	TIM3 global Interrupt
TIM4_IRQn	TIM4 global Interrupt
I2C1_EV_IRQn	I2C1 Event Interrupt
I2C1_ER_IRQn	I2C1 Error Interrupt
I2C2_EV_IRQn	I2C2 Event Interrupt
I2C2_ER_IRQn	I2C2 Error Interrupt
SPI1_IRQn	SPI1 global Interrupt
SPI2_IRQn	SPI2 global Interrupt
USART1_IRQn	USART1 global Interrupt
USART2_IRQn	USART2 global Interrupt
USART3_IRQn	USART3 global Interrupt
EXTI15_10_IRQn	External Line[15:10] Interrupts
RTC_Alarm_IRQn	RTC Alarm through EXTI Line Interrupt
USB_FS_WKUP_IRQn	USB FS WakeUp from suspend through EXTI Line Interrupt
TIM6_IRQn	TIM6 global Interrupt
TIM7_IRQn	TIM7 global Interrupt
SDIO_IRQn	SDIO global Interrupt
TIM5_IRQn	TIM5 global Interrupt
SPI3_IRQn	SPI3 global Interrupt
UART4_IRQn	UART4 global Interrupt
UART5_IRQn	UART5 global Interrupt
DMA2_Channel1_IRQn	DMA2 Channel 1 global Interrupt
DMA2_Channel2_IRQn	DMA2 Channel 2 global Interrupt
DMA2_Channel3_IRQn	DMA2 Channel 3 global Interrupt
DMA2_Channel4_IRQn	DMA2 Channel 4 global Interrupt
DMA2_Channel5_IRQn	DMA2 Channel 5 global Interrupt
AES_IRQn	AES global Interrupt
COMP_ACQ_IRQn	Comparator Channel Acquisition global Interrupt