lpc17xx_gpdma.h File Reference

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Data Structures
struct	gpdma_channel_cfg_t
struct	gpdma_lli_t
Defines
#define	GPDMA_CONN_MCI   1
#define	GPDMA_CONN_SSP0_Tx   2
#define	GPDMA_CONN_SSP0_Rx   3
#define	GPDMA_CONN_SSP1_Tx   4
#define	GPDMA_CONN_SSP1_Rx   5
#define	GPDMA_CONN_SSP2_Tx   6
#define	GPDMA_CONN_SSP2_Rx   7
#define	GPDMA_CONN_ADC   8
#define	GPDMA_CONN_DAC   9
#define	GPDMA_CONN_UART0_Tx   10
#define	GPDMA_CONN_UART0_Rx   11
#define	GPDMA_CONN_UART1_Tx   12
#define	GPDMA_CONN_UART1_Rx   13
#define	GPDMA_CONN_UART2_Tx   14
#define	GPDMA_CONN_UART2_Rx   15
#define	GPDMA_CONN_MAT0_0   16
#define	GPDMA_CONN_MAT0_1   17
#define	GPDMA_CONN_MAT1_0   18
#define	GPDMA_CONN_MAT1_1   19
#define	GPDMA_CONN_MAT2_0   20
#define	GPDMA_CONN_MAT2_1   21
#define	GPDMA_CONN_I2S_Channel_0   22
#define	GPDMA_CONN_I2S_Channel_1   23
#define	GPDMA_CONN_UART3_Tx   26
#define	GPDMA_CONN_UART3_Rx   27
#define	GPDMA_CONN_UART4_Tx   28
#define	GPDMA_CONN_UART4_Rx   29
#define	GPDMA_CONN_MAT3_0   30
#define	GPDMA_CONN_MAT3_1   31
#define	GPDMA_TRANSFERTYPE_M2M   0
#define	GPDMA_TRANSFERTYPE_M2P   1
#define	GPDMA_TRANSFERTYPE_P2M   2
#define	GPDMA_TRANSFERTYPE_P2P   3
#define	GPDMA_TRANSFERTYPE_M2P_DEST_CTRL   5
#define	GPDMA_TRANSFERTYPE_P2M_SRC_CTRL   6
#define	GPDMA_BSIZE_1   0
#define	GPDMA_BSIZE_4   1
#define	GPDMA_BSIZE_8   2
#define	GPDMA_BSIZE_16   3
#define	GPDMA_BSIZE_32   4
#define	GPDMA_BSIZE_64   5
#define	GPDMA_BSIZE_128   6
#define	GPDMA_BSIZE_256   7
#define	GPDMA_WIDTH_BYTE   0
#define	GPDMA_WIDTH_HALFWORD   1
#define	GPDMA_WIDTH_WORD   2
#define	GPDMA_REQSEL_UART   0
#define	GPDMA_REQSEL_TIMER   1
#define	GPDMA_DMACIntStat_Ch(n)   ((1UL << n) & 0xFF)
#define	GPDMA_DMACIntStat_BITMASK   0xFF
#define	GPDMA_DMACIntTCStat_Ch(n)   ((1UL << n) & 0xFF)
#define	GPDMA_DMACIntTCStat_BITMASK   0xFF
#define	GPDMA_DMACIntTCClear_Ch(n)   ((1UL << n) & 0xFF)
#define	GPDMA_DMACIntTCClear_BITMASK   0xFF
#define	GPDMA_DMACIntErrStat_Ch(n)   ((1UL << n) & 0xFF)
#define	GPDMA_DMACIntErrStat_BITMASK   0xFF
#define	GPDMA_DMACIntErrClr_Ch(n)   ((1UL << n) & 0xFF)
#define	GPDMA_DMACIntErrClr_BITMASK   0xFF
#define	GPDMA_DMACRawIntTCStat_Ch(n)   ((1UL << n) & 0xFF)
#define	GPDMA_DMACRawIntTCStat_BITMASK   0xFF
#define	GPDMA_DMACRawIntErrStat_Ch(n)   ((1UL << n) & 0xFF)
#define	GPDMA_DMACRawIntErrStat_BITMASK   0xFF
#define	GPDMA_DMACEnbldChns_Ch(n)   ((1UL << n) & 0xFF)
#define	GPDMA_DMACEnbldChns_BITMASK   0xFF
#define	GPDMA_DMACSoftBReq_Src(n)   ((1UL << n) & 0xFFFF)
#define	GPDMA_DMACSoftBReq_BITMASK   0xFFFF
#define	GPDMA_DMACSoftSReq_Src(n)   ((1UL << n) & 0xFFFF)
#define	GPDMA_DMACSoftSReq_BITMASK   0xFFFF
#define	GPDMA_DMACSoftLBReq_Src(n)   ((1UL << n) & 0xFFFF)
#define	GPDMA_DMACSoftLBReq_BITMASK   0xFFFF
#define	GPDMA_DMACSoftLSReq_Src(n)   ((1UL << n) & 0xFFFF)
#define	GPDMA_DMACSoftLSReq_BITMASK   0xFFFF
#define	GPDMA_DMACConfig_E   0x01
#define	GPDMA_DMACConfig_M   0x02
#define	GPDMA_DMACConfig_BITMASK   0x03
#define	GPDMA_DMACSync_Src(n)   ((1UL << n) & 0xFFFF)
#define	GPDMA_DMACSync_BITMASK   0xFFFF
#define	GPDMA_DMAReqSel_Input(n)   ((1UL << (n - 8)) & 0xFF)
#define	GPDMA_DMAReqSel_BITMASK   0xFF
#define	GPDMA_DMACCxLLI_BITMASK   0xFFFFFFFC
#define	GPDMA_DMACCxControl_TransferSize(n)   ((n & 0xFFF) << 0)
#define	GPDMA_DMACCxControl_SBSize(n)   ((n & 0x07) << 12)
#define	GPDMA_DMACCxControl_DBSize(n)   ((n & 0x07) << 15)
#define	GPDMA_DMACCxControl_SWidth(n)   ((n & 0x07) << 18)
#define	GPDMA_DMACCxControl_DWidth(n)   ((n & 0x07) << 21)
#define	GPDMA_DMACCxControl_SI   (1UL << 26)
#define	GPDMA_DMACCxControl_DI   (1UL << 27)
#define	GPDMA_DMACCxControl_Prot1   (1UL << 28)
#define	GPDMA_DMACCxControl_Prot2   (1UL << 29)
#define	GPDMA_DMACCxControl_Prot3   (1UL << 30)
#define	GPDMA_DMACCxControl_I   (1UL << 31)
#define	GPDMA_DMACCxControl_BITMASK   0xFCFFFFFF
#define	GPDMA_DMACCxConfig_E   (1UL << 0)
#define	GPDMA_DMACCxConfig_SrcPeripheral(n)   ((n & 0x1F) << 1)
#define	GPDMA_DMACCxConfig_DestPeripheral(n)   ((n & 0x1F) << 6)
#define	GPDMA_DMACCxConfig_TransferType(n)   ((n & 0x7) << 11)
#define	GPDMA_DMACCxConfig_IE   (1UL << 14)
#define	GPDMA_DMACCxConfig_ITC   (1UL << 15)
#define	GPDMA_DMACCxConfig_L   (1UL << 16)
#define	GPDMA_DMACCxConfig_A   (1UL << 17)
#define	GPDMA_DMACCxConfig_H   (1UL << 18)
#define	GPDMA_DMACCxConfig_BITMASK   0x7FFFF
Enumerations
enum	gpdma_status_t {   GPDMA_STAT_INT, GPDMA_STAT_INTTC, GPDMA_STAT_INTERR, GPDMA_STAT_RAWINTTC,   GPDMA_STAT_RAWINTERR, GPDMA_STAT_ENABLED_CH }
enum	gpdma_state_clear_t { GPDMA_STATCLR_INTTC, GPDMA_STATCLR_INTERR }
Functions
void	Lpc17xxGPDMA_Init (void)
	Initialize GPDMA controller.
int	Lpc17xxGPDMA_Setup (gpdma_channel_cfg_t *ch_config)
	Setup GPDMA channel.
int	Lpc17xxGPDMA_IntGetStatus (gpdma_status_t type, uint8_t ch)
	Check interrupt status.
void	Lpc17xxGPDMA_ClearIntPending (gpdma_state_clear_t type, uint8_t ch)
	Clear one or more interrupt requests on DMA channels.
void	Lpc17xxGPDMA_ChannelCmd (uint8_t ch, int enabled)
	Enable/Disable DMA channel.

---

Define Documentation

#define GPDMA_CONN_MCI   1

 * $Id: $
 * 

#define GPDMA_CONN_SSP0_Tx   2

#define GPDMA_CONN_SSP0_Rx   3

#define GPDMA_CONN_SSP1_Tx   4

#define GPDMA_CONN_SSP1_Rx   5

#define GPDMA_CONN_SSP2_Tx   6

#define GPDMA_CONN_SSP2_Rx   7

#define GPDMA_CONN_ADC   8

#define GPDMA_CONN_DAC   9

#define GPDMA_CONN_UART0_Tx   10

#define GPDMA_CONN_UART0_Rx   11

#define GPDMA_CONN_UART1_Tx   12

#define GPDMA_CONN_UART1_Rx   13

#define GPDMA_CONN_UART2_Tx   14

#define GPDMA_CONN_UART2_Rx   15

#define GPDMA_CONN_MAT0_0   16

#define GPDMA_CONN_MAT0_1   17

#define GPDMA_CONN_MAT1_0   18

#define GPDMA_CONN_MAT1_1   19

#define GPDMA_CONN_MAT2_0   20

#define GPDMA_CONN_MAT2_1   21

#define GPDMA_CONN_I2S_Channel_0   22

#define GPDMA_CONN_I2S_Channel_1   23

#define GPDMA_CONN_UART3_Tx   26

#define GPDMA_CONN_UART3_Rx   27

#define GPDMA_CONN_UART4_Tx   28

#define GPDMA_CONN_UART4_Rx   29

#define GPDMA_CONN_MAT3_0   30

#define GPDMA_CONN_MAT3_1   31

#define GPDMA_TRANSFERTYPE_M2M   0

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_TRANSFERTYPE_M2P   1

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_TRANSFERTYPE_P2M   2

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_TRANSFERTYPE_P2P   3

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_TRANSFERTYPE_M2P_DEST_CTRL   5

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_TRANSFERTYPE_P2M_SRC_CTRL   6

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_BSIZE_1   0

#define GPDMA_BSIZE_4   1

#define GPDMA_BSIZE_8   2

#define GPDMA_BSIZE_16   3

#define GPDMA_BSIZE_32   4

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_BSIZE_64   5

#define GPDMA_BSIZE_128   6

#define GPDMA_BSIZE_256   7

#define GPDMA_WIDTH_BYTE   0

#define GPDMA_WIDTH_HALFWORD   1

#define GPDMA_WIDTH_WORD   2

#define GPDMA_REQSEL_UART   0

#define GPDMA_REQSEL_TIMER   1

#define GPDMA_DMACIntStat_Ch

(

n

)

((1UL << n) & 0xFF)

Referenced by Lpc17xxGPDMA_IntGetStatus().

#define GPDMA_DMACIntStat_BITMASK   0xFF

#define GPDMA_DMACIntTCStat_Ch

(

n

)

((1UL << n) & 0xFF)

Referenced by Lpc17xxGPDMA_IntGetStatus().

#define GPDMA_DMACIntTCStat_BITMASK   0xFF

#define GPDMA_DMACIntTCClear_Ch

(

n

)

((1UL << n) & 0xFF)

Referenced by Lpc17xxGPDMA_ClearIntPending(), Lpc17xxGPDMA_IntGetStatus(), and Lpc17xxGPDMA_Setup().

#define GPDMA_DMACIntTCClear_BITMASK   0xFF

#define GPDMA_DMACIntErrStat_Ch

(

n

)

((1UL << n) & 0xFF)

#define GPDMA_DMACIntErrStat_BITMASK   0xFF

#define GPDMA_DMACIntErrClr_Ch

(

n

)

((1UL << n) & 0xFF)

Referenced by Lpc17xxGPDMA_ClearIntPending(), and Lpc17xxGPDMA_Setup().

#define GPDMA_DMACIntErrClr_BITMASK   0xFF

#define GPDMA_DMACRawIntTCStat_Ch

(

n

)

((1UL << n) & 0xFF)

Referenced by Lpc17xxGPDMA_IntGetStatus().

#define GPDMA_DMACRawIntTCStat_BITMASK   0xFF

#define GPDMA_DMACRawIntErrStat_Ch

(

n

)

((1UL << n) & 0xFF)

Referenced by Lpc17xxGPDMA_IntGetStatus().

#define GPDMA_DMACRawIntErrStat_BITMASK   0xFF

#define GPDMA_DMACEnbldChns_Ch

(

n

)

((1UL << n) & 0xFF)

Referenced by Lpc17xxGPDMA_IntGetStatus(), and Lpc17xxGPDMA_Setup().

#define GPDMA_DMACEnbldChns_BITMASK   0xFF

#define GPDMA_DMACSoftBReq_Src

(

n

)

((1UL << n) & 0xFFFF)

#define GPDMA_DMACSoftBReq_BITMASK   0xFFFF

#define GPDMA_DMACSoftSReq_Src

(

n

)

((1UL << n) & 0xFFFF)

#define GPDMA_DMACSoftSReq_BITMASK   0xFFFF

#define GPDMA_DMACSoftLBReq_Src

(

n

)

((1UL << n) & 0xFFFF)

#define GPDMA_DMACSoftLBReq_BITMASK   0xFFFF

#define GPDMA_DMACSoftLSReq_Src

(

n

)

((1UL << n) & 0xFFFF)

#define GPDMA_DMACSoftLSReq_BITMASK   0xFFFF

#define GPDMA_DMACConfig_E   0x01

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_DMACConfig_M   0x02

#define GPDMA_DMACConfig_BITMASK   0x03

#define GPDMA_DMACSync_Src

(

n

)

((1UL << n) & 0xFFFF)

#define GPDMA_DMACSync_BITMASK   0xFFFF

#define GPDMA_DMAReqSel_Input

(

n

)

((1UL << (n - 8)) & 0xFF)

#define GPDMA_DMAReqSel_BITMASK   0xFF

#define GPDMA_DMACCxLLI_BITMASK   0xFFFFFFFC

#define GPDMA_DMACCxControl_TransferSize

(

n

)

((n & 0xFFF) << 0)

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_DMACCxControl_SBSize

(

n

)

((n & 0x07) << 12)

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_DMACCxControl_DBSize

(

n

)

((n & 0x07) << 15)

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_DMACCxControl_SWidth

(

n

)

((n & 0x07) << 18)

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_DMACCxControl_DWidth

(

n

)

((n & 0x07) << 21)

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_DMACCxControl_SI   (1UL << 26)

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_DMACCxControl_DI   (1UL << 27)

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_DMACCxControl_Prot1   (1UL << 28)

#define GPDMA_DMACCxControl_Prot2   (1UL << 29)

#define GPDMA_DMACCxControl_Prot3   (1UL << 30)

#define GPDMA_DMACCxControl_I   (1UL << 31)

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_DMACCxControl_BITMASK   0xFCFFFFFF

#define GPDMA_DMACCxConfig_E   (1UL << 0)

Referenced by Lpc17xxGPDMA_ChannelCmd().

#define GPDMA_DMACCxConfig_SrcPeripheral

(

n

)

((n & 0x1F) << 1)

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_DMACCxConfig_DestPeripheral

(

n

)

((n & 0x1F) << 6)

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_DMACCxConfig_TransferType

(

n

)

((n & 0x7) << 11)

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_DMACCxConfig_IE   (1UL << 14)

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_DMACCxConfig_ITC   (1UL << 15)

Referenced by Lpc17xxGPDMA_Setup().

#define GPDMA_DMACCxConfig_L   (1UL << 16)

#define GPDMA_DMACCxConfig_A   (1UL << 17)

#define GPDMA_DMACCxConfig_H   (1UL << 18)

#define GPDMA_DMACCxConfig_BITMASK   0x7FFFF

---

Enumeration Type Documentation

enum gpdma_status_t

Enumerator:

GPDMA_STAT_INT
GPDMA_STAT_INTTC
GPDMA_STAT_INTERR
GPDMA_STAT_RAWINTTC
GPDMA_STAT_RAWINTERR
GPDMA_STAT_ENABLED_CH

enum gpdma_state_clear_t

Enumerator:

GPDMA_STATCLR_INTTC
GPDMA_STATCLR_INTERR

---

Function Documentation

void Lpc17xxGPDMA_Init

(

void

)

Initialize GPDMA controller.

Parameters:

none

Returns:

none

References CLKPWR_PCONP_PCGPDMA, LPC_GPDMA, LPC_GPDMACH0, LPC_GPDMACH1, LPC_GPDMACH2, LPC_GPDMACH3, LPC_GPDMACH4, LPC_GPDMACH5, LPC_GPDMACH6, LPC_GPDMACH7, and SysCtlPeripheralClkEnable.

int Lpc17xxGPDMA_Setup

(

gpdma_channel_cfg_t *

ch_config

)

Setup GPDMA channel.

Setup GPDMA channel peripheral according to the specified parameters in the ch_config.

Parameters:

ch_config

Pointer to a gpdma_channel_cfg_t structure that contains the configuration information for the specified GPDMA channel peripheral.

Returns:

0 on success, -1 in case of an error

References LPC_GPDMACH_TypeDef::CConfig, LPC_GPDMACH_TypeDef::CControl, LPC_GPDMACH_TypeDef::CDestAddr, gpdma_channel_cfg_t::ch, LPC_GPDMACH_TypeDef::CLLI, LPC_GPDMACH_TypeDef::CSrcAddr, gpdma_channel_cfg_t::dma_lli, gpdma_channel_cfg_t::dst_addr, gpdma_channel_cfg_t::dst_conn, GPDMA_BSIZE_32, GPDMA_DMACConfig_E, GPDMA_DMACCxConfig_DestPeripheral, GPDMA_DMACCxConfig_IE, GPDMA_DMACCxConfig_ITC, GPDMA_DMACCxConfig_SrcPeripheral, GPDMA_DMACCxConfig_TransferType, GPDMA_DMACCxControl_DBSize, GPDMA_DMACCxControl_DI, GPDMA_DMACCxControl_DWidth, GPDMA_DMACCxControl_I, GPDMA_DMACCxControl_SBSize, GPDMA_DMACCxControl_SI, GPDMA_DMACCxControl_SWidth, GPDMA_DMACCxControl_TransferSize, GPDMA_DMACEnbldChns_Ch, GPDMA_DMACIntErrClr_Ch, GPDMA_DMACIntTCClear_Ch, GPDMA_LUTPerAddr, GPDMA_TRANSFERTYPE_M2M, GPDMA_TRANSFERTYPE_M2P, GPDMA_TRANSFERTYPE_M2P_DEST_CTRL, GPDMA_TRANSFERTYPE_P2M, GPDMA_TRANSFERTYPE_P2M_SRC_CTRL, GPDMA_TRANSFERTYPE_P2P, LPC_GPDMA, LPC_SC, gpdma_channel_cfg_t::src_addr, gpdma_channel_cfg_t::src_conn, gpdma_channel_cfg_t::transfer_size, gpdma_channel_cfg_t::transfer_type, and gpdma_channel_cfg_t::transfer_width.

int Lpc17xxGPDMA_IntGetStatus	(	gpdma_status_t	type,
		uint8_t	ch
	)

Check interrupt status.

Check if corresponding channel does have an active interrupt request or not

Parameters:

type	type of status, should be: GPDMA_STAT_INT: GPDMA Interrupt Status GPDMA_STAT_INTTC: GPDMA Interrupt Terminal Count Request Status GPDMA_STAT_INTERR: GPDMA Interrupt Error Status GPDMA_STAT_RAWINTTC: GPDMA Raw Interrupt Terminal Count Status GPDMA_STAT_RAWINTERR: GPDMA Raw Error Interrupt Status GPDMA_STAT_ENABLED_CH:GPDMA Enabled Channel Status
ch	GPDMA channel, should be in range from 0 to 7

Returns:

status of DMA channel interrupt after masking 1: the corresponding channel has no active interrupt request 0: the corresponding channel does have an active interrupt request

References GPDMA_DMACEnbldChns_Ch, GPDMA_DMACIntStat_Ch, GPDMA_DMACIntTCClear_Ch, GPDMA_DMACIntTCStat_Ch, GPDMA_DMACRawIntErrStat_Ch, GPDMA_DMACRawIntTCStat_Ch, GPDMA_STAT_INT, GPDMA_STAT_INTERR, GPDMA_STAT_INTTC, GPDMA_STAT_RAWINTERR, GPDMA_STAT_RAWINTTC, and LPC_GPDMA.

void Lpc17xxGPDMA_ClearIntPending	(	gpdma_state_clear_t	type,
		uint8_t	ch
	)

Clear one or more interrupt requests on DMA channels.

Parameters:

type	type of status, should be: GPDMA_STATCLR_INTTC: GPDMA Interrupt Terminal Count Request Clear GPDMA_STATCLR_INTERR: GPDMA Interrupt Error Clear
ch	GPDMA channel, should be in range from 0 to 7

Returns:

none

References GPDMA_DMACIntErrClr_Ch, GPDMA_DMACIntTCClear_Ch, GPDMA_STATCLR_INTTC, and LPC_GPDMA.

void Lpc17xxGPDMA_ChannelCmd	(	uint8_t	ch,
		int	enabled
	)

Enable/Disable DMA channel.

Setup GPDMA channel peripheral according to the specified parameters in the ch_config.

Parameters:

ch	GPDMA channel, should be in range from 0 to 7
enabled	New state of this channel: 1: enabled, 0: disabled

Returns:

none

References LPC_GPDMACH_TypeDef::CConfig, and GPDMA_DMACCxConfig_E.