System Control InterFace(SCIF) driver interface. More...

#include "compiler.h"

Include dependency graph for scif_uc3l.h:

This graph shows which files directly or indirectly include this file:

Data Structures
struct	scif_osc_opt_t
	OSC0/OSC1 startup options. More...
struct	scif_osc32_opt_t
	OSC32 startup options. More...
struct	scif_gclk_opt_t
	Generic clock generation settings. More...
struct	scif_dfll_openloop_conf_t
	DFLL open-loop mode settings. More...
struct	scif_dfll_closedloop_conf_t
	DFLL closed-loop mode settings. More...
struct	scif_dfll_ssg_conf_t
	DFLL SSG settings. More...
Defines
#define	AVR32_SCIF_OSCCTRL0_OSCEN_ENABLE 0x00000001
#define	AVR32_SCIF_OSCCTRL0_OSCEN_DISABLE 0x00000000
#define	AVR32_SCIF_OSCCTRL32_OSC32EN_ENABLE 0x00000001
#define	AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE 0x00000000
#define	SCIF_EXT_CRYSTAL_MIN_FREQ_HZ 4000000UL
	Device-specific data.
#define	SCIF_EXT_CRYSTAL_MAX_FREQ_HZ 20000000UL
#define	SCIF_DFLL_MINFREQ_KHZ 40000
	The min DFLL output frequency.
#define	SCIF_DFLL_MINFREQ_HZ 40000000UL
#define	SCIF_DFLL_MAXFREQ_KHZ 150000
	The max DFLL output frequency.
#define	SCIF_DFLL_MAXFREQ_HZ 150000000UL
#define	SCIF_SLOWCLOCK_FREQ_HZ AVR32_SCIF_RCOSC_FREQUENCY
	The RCSYS slow clock frequency.
#define	SCIF_SLOWCLOCK_FREQ_KHZ (SCIF_SLOWCLOCK_FREQ_HZ/1000)
#define	SCIF_RC32K_FREQ_HZ 32768
	The RC32K slow clock frequency.
#define	SCIF_RC32K_FREQ_KHZ (SCIF_RC32K_FREQ_HZ/1000)
#define	SCIF_RC120M_FREQ_HZ 120000000UL
	The RC120M frequency.
#define	SCIF_RC120M_FREQ_KHZ 120000
#define	SCIF_OSC32_FREQ_HZ 32768
	The OSC32 frequency.
#define	SCIF_POLL_TIMEOUT 100000
	The timeguard used for polling in ticks.
#define	SCIF_NOT_SUPPORTED (-10000)
	Define "not supported" for the chosen implementation.
#define	SCIF_UNLOCK(reg) (AVR32_SCIF.unlock = (AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET)\|(reg))
	Unlock SCIF register macro.
Enumerations
enum	scif_gcctrl_oscsel_t { SCIF_GCCTRL_SLOWCLOCK = AVR32_SCIF_GC_USES_CLK_SLOW, SCIF_GCCTRL_OSC32K = AVR32_SCIF_GC_USES_CLK_32, SCIF_GCCTRL_DFLL0 = AVR32_SCIF_GC_USES_DFLL0, SCIF_GCCTRL_OSC0 = AVR32_SCIF_GC_USES_OSC0, SCIF_GCCTRL_RC120M = AVR32_SCIF_GC_USES_RC120M, SCIF_GCCTRL_CPUCLOCK = AVR32_SCIF_GC_USES_CLK_CPU, SCIF_GCCTRL_HSBCLOCK = AVR32_SCIF_GC_USES_CLK_HSB, SCIF_GCCTRL_PBACLOCK = AVR32_SCIF_GC_USES_CLK_PBA, SCIF_GCCTRL_PBBCLOCK = AVR32_SCIF_GC_USES_CLK_PBB, SCIF_GCCTRL_RC32K = AVR32_SCIF_GC_USES_RC32K, SCIF_GCCTRL_CLK1K = AVR32_SCIF_GC_USES_CLK_1K, SCIF_GCCTRL_OSCSEL_INVALID }
	The different clock source for the generic clocks. More...
enum	scif_osc_t { SCIF_OSC0 = 0, SCIF_OSC1 = 1 }
	The different oscillators. More...
enum	scif_osc_mode_t { SCIF_OSC_MODE_EXT_CLK = 0, SCIF_OSC_MODE_2PIN_CRYSTAL = 1, SCIF_OSC_MODE_NOT_SUPPORTED_1 = 2, SCIF_OSC_MODE_NOT_SUPPORTED_2 = 3, SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR = 4, SCIF_OSC_MODE_NOT_SUPPORTED_3 = 5, SCIF_OSC_MODE_NOT_SUPPORTED_4 = 6, SCIF_OSC_MODE_NOT_SUPPORTED_5 = 7 }
	The different oscillator modes. More...
OSC0/OSC1 Functions
long int	scif_start_osc (scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready)
	Configure and start an OSC0/OSC1 oscillator.
bool	scif_is_osc_ready (scif_osc_t osc)
	Is an oscillator stable and ready to be used as clock source?
long int	scif_stop_osc (scif_osc_t osc)
	Stop an oscillator.
long int	scif_configure_osc_crystalmode (scif_osc_t osc, unsigned int fcrystal)
	Configure an oscillator in crystal mode.
long int	scif_configure_osc_extmode (scif_osc_t osc)
	Configure an external clock as input clock.
long int	scif_enable_osc (scif_osc_t osc, unsigned int startup, bool wait_for_ready)
	Enable an oscillator with a given startup time.
OSC32 Functions
long int	scif_start_osc32 (const scif_osc32_opt_t *opt, bool wait_for_ready)
	Configure and start the OSC32 oscillator.
long int	scif_stop_osc32 (void)
	Stop the OSC32 oscillator.
DFLL Control Functions
#define	scif_dfll0_ssg_gc_enable(pgc_conf) scif_start_gclk(AVR32_SCIF_GCLK_DFLL0_SSG, pgc_conf)
	Configure and enable the SSG reference generic clock.
#define	scif_dfll0_closedloop_mainref_gc_enable(pgc_conf) scif_start_gclk(AVR32_SCIF_GCLK_DFLL0_REF, pgc_conf)
	Configure and enable the closed-loop mode main reference generic clock.
#define	scif_dfll0_closedloop_dither_gc_enable(pgc_conf) scif_dfll0_ssg_gc_enable(pgc_conf)
	Configure and enable the generic clock used by the closed-loop mode dithering stage and by the SSG.
long int	scif_dfll0_openloop_start (const scif_dfll_openloop_conf_t *pdfllconfig)
	Configure and start the DFLL0 in open loop mode.
long int	scif_dfll0_openloop_start_auto (unsigned long TargetFreqkHz)
	Automatic configuration and start of the DFLL0 in open loop mode.
long int	scif_dfll0_openloop_updatefreq (const scif_dfll_openloop_conf_t *pdfllconfig)
	Update the frequency of the DFLL0 in open loop mode.
long int	scif_dfll0_openloop_updatefreq_auto (unsigned long TargetFreq)
	Automatic configuration to update the frequency of the DFLL0 in open loop mode.
long int	scif_dfll0_openloop_stop (void)
	Stop the DFLL0 in open loop mode.
long int	scif_dfll0_ssg_enable (scif_dfll_ssg_conf_t *pssg_conf)
	Configure and enable the SSG.
long int	scif_dfll0_closedloop_start (const scif_dfll_closedloop_conf_t *pdfllconfig)
	Configure and start the DFLL0 in closed loop mode.
long int	scif_dfll0_closedloop_configure_and_start (const scif_gclk_opt_t *gc_dfllif_ref_opt, unsigned long long target_freq_hz, bool enable_ssg)
	Depending on the target frequency, compute the DFLL configuration parameters and start the DFLL0 in closed loop mode.
120MHz RCosc Functions
void	scif_start_rc120M (void)
	Start the 120MHz internal RCosc (RC120M) clock.
void	scif_stop_rc120M (void)
	Stop the 120MHz internal RCosc (RC120M) clock.
32kHz internal RCosc (RC32K) Functions
void	scif_start_rc32k (void)
	Start the 32kHz internal RCosc (RC32K) clock.
void	scif_stop_rc32k (void)
	Stop the 32kHz internal RCosc (RC32K) clock.
void	scif_disable_rc32out (void)
	Unforce the RC32 signal from being output on the dedicated pin (PA20)
Generic Clock Functions
long int	scif_start_gclk (unsigned int gclk, const scif_gclk_opt_t *opt)
	Setup and start a generic clock.
long int	scif_stop_gclk (unsigned int gclk)
	Stop a generic clock.
long int	scif_gc_setup (unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor)
	Setup a generic clock.
long int	scif_gc_enable (unsigned int gclk)
	Enable a generic clock.
Miscellaneous Functions
long int	scif_pclksr_statushigh_wait (unsigned long statusMask)
	Wait for a status high in the Power and Clocks status register.

Detailed Description

System Control InterFace(SCIF) driver interface.

Compiler: IAR EWAVR32 and GNU GCC for AVR32
Supported devices: All AVR32 UC3L devices.
AppNote:

Author:: Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Define Documentation

#define AVR32_SCIF_OSCCTRL0_OSCEN_ENABLE 0x00000001

#define AVR32_SCIF_OSCCTRL0_OSCEN_DISABLE 0x00000000

#define AVR32_SCIF_OSCCTRL32_OSC32EN_ENABLE 0x00000001

#define AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE 0x00000000

#define SCIF_EXT_CRYSTAL_MIN_FREQ_HZ 4000000UL

Device-specific data.

< External crystal/clock min frequency (in Herz) External crystal/clock max frequency (in Herz)

Referenced by scif_start_osc(), and scif_start_osc32().

#define SCIF_EXT_CRYSTAL_MAX_FREQ_HZ 20000000UL

Referenced by scif_start_osc(), and scif_start_osc32().

#define SCIF_DFLL_MINFREQ_KHZ 40000

The min DFLL output frequency.

#define SCIF_DFLL_MINFREQ_HZ 40000000UL

#define SCIF_DFLL_MAXFREQ_KHZ 150000

The max DFLL output frequency.

#define SCIF_DFLL_MAXFREQ_HZ 150000000UL

#define SCIF_SLOWCLOCK_FREQ_HZ AVR32_SCIF_RCOSC_FREQUENCY

The RCSYS slow clock frequency.

Referenced by scif_dfll0_closedloop_configure_and_start().

#define SCIF_SLOWCLOCK_FREQ_KHZ (SCIF_SLOWCLOCK_FREQ_HZ/1000)

#define SCIF_RC32K_FREQ_HZ 32768

The RC32K slow clock frequency.

Referenced by scif_dfll0_closedloop_configure_and_start().

#define SCIF_RC32K_FREQ_KHZ (SCIF_RC32K_FREQ_HZ/1000)

#define SCIF_RC120M_FREQ_HZ 120000000UL

The RC120M frequency.

Referenced by scif_dfll0_closedloop_configure_and_start().

#define SCIF_RC120M_FREQ_KHZ 120000

#define SCIF_OSC32_FREQ_HZ 32768

The OSC32 frequency.

#define SCIF_POLL_TIMEOUT 100000

The timeguard used for polling in ticks.

Referenced by scif_pclksr_statushigh_wait(), and scif_stop_gclk().

#define SCIF_NOT_SUPPORTED (-10000)

Define "not supported" for the chosen implementation.

#define SCIF_UNLOCK ( reg ) (AVR32_SCIF.unlock = (AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET)|(reg))

Unlock SCIF register macro.

#define scif_dfll0_ssg_gc_enable ( pgc_conf ) scif_start_gclk(AVR32_SCIF_GCLK_DFLL0_SSG, pgc_conf)

Configure and enable the SSG reference generic clock.

Note:: The frequency of the SSG reference clock should be higher than the CLK_DFLLIF_REF to ensure that the DFLLIF can lock.

Parameters:

pgc_conf The settings for the generic clock [INPUT]

Returns:: Status.

Return values:

0	SSG Generic clock configured and started successfully.
<0	Error.

#define scif_dfll0_closedloop_mainref_gc_enable ( pgc_conf ) scif_start_gclk(AVR32_SCIF_GCLK_DFLL0_REF, pgc_conf)

Configure and enable the closed-loop mode main reference generic clock.

Parameters:

pgc_conf The settings for the generic clock [INPUT]

Returns:: Status.

Return values:

0	Main reference generic clock configured and started successfully.
<0	Error.

Referenced by scif_dfll0_closedloop_configure_and_start().

#define scif_dfll0_closedloop_dither_gc_enable ( pgc_conf ) scif_dfll0_ssg_gc_enable(pgc_conf)

Configure and enable the generic clock used by the closed-loop mode dithering stage and by the SSG.

Parameters:

pgc_conf The settings for the generic clock [INPUT]

Returns:: Status.

Return values:

0	Dithering & SSG reference generic clock configured and started successfully.
<0	Error.

Enumeration Type Documentation

enum scif_gcctrl_oscsel_t

The different clock source for the generic clocks.

Enumerator:

SCIF_GCCTRL_SLOWCLOCK
SCIF_GCCTRL_OSC32K
SCIF_GCCTRL_DFLL0
SCIF_GCCTRL_OSC0
SCIF_GCCTRL_RC120M
SCIF_GCCTRL_CPUCLOCK
SCIF_GCCTRL_HSBCLOCK
SCIF_GCCTRL_PBACLOCK
SCIF_GCCTRL_PBBCLOCK
SCIF_GCCTRL_RC32K
SCIF_GCCTRL_CLK1K
SCIF_GCCTRL_OSCSEL_INVALID

enum scif_osc_t

The different oscillators.

Enumerator:

SCIF_OSC0
SCIF_OSC1

enum scif_osc_mode_t

The different oscillator modes.

Enumerator:

SCIF_OSC_MODE_EXT_CLK
SCIF_OSC_MODE_2PIN_CRYSTAL
SCIF_OSC_MODE_NOT_SUPPORTED_1
SCIF_OSC_MODE_NOT_SUPPORTED_2
SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR
SCIF_OSC_MODE_NOT_SUPPORTED_3
SCIF_OSC_MODE_NOT_SUPPORTED_4
SCIF_OSC_MODE_NOT_SUPPORTED_5

Function Documentation

long int scif_start_osc	(	scif_osc_t	osc,
		const scif_osc_opt_t *	opt,
		bool	wait_for_ready
	)

Configure and start an OSC0/OSC1 oscillator.

Parameters:

osc	The oscillator to start [INPUT]
opt	The configuration of the oscillator [INPUT]
wait_for_ready	Wait for the oscillator to be stable before return [INPUT]

Note:: To avoid an infinite loop, this function checks the osc0 ready flag SCIF_POLL_TIMEOUT times.

Returns:: Status.

Return values:

0	Oscillator start successfull.
<0	Error starting the oscillator.

Interrupt Functions Power and Clocks Status Functions OSC0/OSC1 Functions

References ENABLE, scif_osc_opt_t::freq_hz, scif_osc_opt_t::gain, scif_osc_opt_t::mode, u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, SCIF_EXT_CRYSTAL_MAX_FREQ_HZ, SCIF_EXT_CRYSTAL_MIN_FREQ_HZ, SCIF_OSC_MODE_2PIN_CRYSTAL, SCIF_OSC_MODE_EXT_CLK, scif_pclksr_statushigh_wait(), SCIF_UNLOCK, and scif_osc_opt_t::startup.

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bool scif_is_osc_ready ( scif_osc_t osc )

Is an oscillator stable and ready to be used as clock source?

Parameters:

osc	The oscillator [INPUT]

Returns:: Status.

Return values:

true	oscillator stable and ready
false	oscillator not enabled or not ready.

long int scif_stop_osc ( scif_osc_t osc )

Stop an oscillator.

Parameters:

osc	The oscillator to stop

Returns:: Status.

Return values:

0	Oscillator successfully stopped.
<0	An error occured when stopping the oscillator.

References SCIF_UNLOCK.

long int scif_configure_osc_crystalmode	(	scif_osc_t	osc,
		unsigned int	fcrystal
	)

Configure an oscillator in crystal mode.

Parameters:

osc	The oscillator to configure [INPUT]
fcrystal	Crystal frequency (Hz) [INPUT]

Returns:: Status.

Return values:

0	Oscillator successfully configured.
<0	Error configuring the oscillator.

References u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, SCIF_OSC_MODE_2PIN_CRYSTAL, and SCIF_UNLOCK.

long int scif_configure_osc_extmode ( scif_osc_t osc )

Configure an external clock as input clock.

Parameters:

osc	The external clock to configure [INPUT]

Returns:: Status.

Return values:

0	External clock successfully configured.
<0	Error configuring the external clock.

References u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, SCIF_OSC_MODE_EXT_CLK, and SCIF_UNLOCK.

long int scif_enable_osc	(	scif_osc_t	osc,
		unsigned int	startup,
		bool	wait_for_ready
	)

Enable an oscillator with a given startup time.

Parameters:

osc	The oscillator to configure [INPUT]
startup	Oscillator startup time (one of AVR32_SCIF_OSCCTRLx_STARTUP_x_RCOSC) [INPUT]
wait_for_ready	Wait for the oscillator to be stable before return [INPUT]

Returns:: Status.

Return values:

0	Oscillator successfully started
<0	Error starting the oscillator.

References ENABLE, u_avr32_scif_oscctrl0_t::oscctrl0, u_avr32_scif_oscctrl0_t::OSCCTRL0, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

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long int scif_start_osc32	(	const scif_osc32_opt_t *	opt,
		bool	wait_for_ready
	)

Configure and start the OSC32 oscillator.

Parameters:

opt	The configuration of the oscillator [INPUT]
wait_for_ready	Wait for the oscillator to be stable before return [INPUT]

Note:: To avoid an infinite loop, this function checks the osc32 ready flag SCIF_POLL_TIMEOUT times.

Returns:: Status.

Return values:

0	Oscillator start successfull.
<0	Error starting the oscillator.

OSC32 Functions

References scif_osc32_opt_t::en1k, scif_osc32_opt_t::en32k, ENABLE, scif_osc32_opt_t::mode, u_avr32_scif_oscctrl32_t::oscctrl32, u_avr32_scif_oscctrl32_t::OSCCTRL32, scif_osc32_opt_t::pinsel, scif_disable_rc32out(), SCIF_EXT_CRYSTAL_MAX_FREQ_HZ, SCIF_EXT_CRYSTAL_MIN_FREQ_HZ, SCIF_OSC_MODE_2PIN_CRYSTAL, SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR, SCIF_OSC_MODE_EXT_CLK, scif_pclksr_statushigh_wait(), SCIF_UNLOCK, and scif_osc32_opt_t::startup.

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long int scif_stop_osc32 ( void )

Stop the OSC32 oscillator.

Returns:: Status.

Return values:

0	Oscillator successfully stopped.
<0	An error occured when stopping the oscillator.

References SCIF_UNLOCK.

long int scif_dfll0_openloop_start ( const scif_dfll_openloop_conf_t * pdfllconfig )

Configure and start the DFLL0 in open loop mode.

Parameters:

pdfllconfig The DFLL parameters in open loop mode [INPUT]

Returns:: Status.

Return values:

0	DFLL0 configured and started successfully.
<0	Error.

References scif_dfll_openloop_conf_t::coarse, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, ENABLE, scif_dfll_openloop_conf_t::fine, SCIF_DFLL0_MODE_OPENLOOP, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

Referenced by scif_dfll0_openloop_start_auto().

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long int scif_dfll0_openloop_start_auto ( unsigned long TargetFreqkHz )

Automatic configuration and start of the DFLL0 in open loop mode.

Parameters:

TargetFreqkHz The DFLL target frequency (in kHz) [INPUT]

Returns:: Status.

Return values:

0	DFLL0 configured and started successfully.
<0	Error.

References scif_dfll_openloop_conf_t::coarse, scif_dfll_openloop_conf_t::fine, scif_dfll0_openloop_start(), SCIF_DFLL_COARSE_MAX, SCIF_DFLL_FINE_HALF, SCIF_DFLL_FINE_MAX, SCIF_DFLL_MAXFREQ_KHZ, and SCIF_DFLL_MINFREQ_KHZ.

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long int scif_dfll0_openloop_updatefreq ( const scif_dfll_openloop_conf_t * pdfllconfig )

Update the frequency of the DFLL0 in open loop mode.

Parameters:

pdfllconfig The DFLL parameters in open loop mode [INPUT]

Returns:: Status.

Return values:

0	DFLL0 frequency updated successfully.
<0	Error.

References scif_dfll_openloop_conf_t::coarse, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, scif_dfll_openloop_conf_t::fine, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

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long int scif_dfll0_openloop_updatefreq_auto ( unsigned long TargetFreq )

Automatic configuration to update the frequency of the DFLL0 in open loop mode.

Parameters:

TargetFreq The DFLL target frequency (in kHz) [INPUT]

Returns:: Status.

Return values:

0	DFLL0 frequency updated successfully.
<0	Error.

long int scif_dfll0_openloop_stop ( void )

Stop the DFLL0 in open loop mode.

Returns:: Status.

Return values:

0	DFLL0 successfully stopped.
<0	Error.

References u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

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long int scif_dfll0_ssg_enable ( scif_dfll_ssg_conf_t * pssg_conf )

Configure and enable the SSG.

Note:: The SSG reference generic clock must have previously been enabled.

Parameters:

pssg_conf The settings for the SCIF.DFLL0SSG register [INPUT]

Returns:: Status.

Return values:

0	SSG Generic clock configured and started successfully.
<0	Error.

References scif_dfll_ssg_conf_t::amplitude, u_avr32_scif_dfll0ssg_t::dfll0ssg, u_avr32_scif_dfll0ssg_t::DFLL0SSG, ENABLE, SCIF_UNLOCK, scif_dfll_ssg_conf_t::step_size, and scif_dfll_ssg_conf_t::use_random.

long int scif_dfll0_closedloop_start ( const scif_dfll_closedloop_conf_t * pdfllconfig )

Configure and start the DFLL0 in closed loop mode.

Note:: The main reference generic clock must have previously been started.

Parameters:

pdfllconfig The DFLL parameters in closed loop mode [INPUT]

Returns:: Status.

Return values:

0	DFLL0 configured and started successfully.
<0	Error.

References scif_dfll_closedloop_conf_t::coarse, scif_dfll_closedloop_conf_t::coarsemaxstep, u_avr32_scif_dfll0conf_t::dfll0conf, u_avr32_scif_dfll0conf_t::DFLL0CONF, ENABLE, scif_dfll_closedloop_conf_t::finemaxstep, scif_dfll_closedloop_conf_t::fmul, scif_dfll_closedloop_conf_t::imul, SCIF_DFLL0_MODE_CLOSEDLOOP, scif_pclksr_statushigh_wait(), and SCIF_UNLOCK.

Referenced by scif_dfll0_closedloop_configure_and_start().

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long int scif_dfll0_closedloop_configure_and_start	(	const scif_gclk_opt_t *	gc_dfllif_ref_opt,
		unsigned long long	target_freq_hz,
		bool	enable_ssg
	)

Depending on the target frequency, compute the DFLL configuration parameters and start the DFLL0 in closed loop mode.

Note:: Configures and enables the generic clock CLK_DFLLIF_REF to serve as the main reference.; This function only supports the following source clocks for the CLK_DFLLIF_REF generic clock: SCIF_GCCTRL_SLOWCLOCK (aka RCSYS), SCIF_GCCTRL_OSC32K, SCIF_GCCTRL_RC32K, SCIF_GCCTRL_OSC0, SCIF_GCCTRL_RC120M, SCIF_GCCTRL_CLK1K.

Parameters:

gc_dfllif_ref_opt	The settings for the CLK_DFLLIF_REF generic clock [INPUT]
target_freq_hz	The target frequency (in Hz) [INPUT]
enable_ssg	Enable/disable the SSG feature [INPUT]

Returns:: Status.

Return values:

0	DFLL0 configured and started successfully.
<0	Error.

References scif_gclk_opt_t::clock_source, scif_dfll_closedloop_conf_t::coarse, scif_dfll_closedloop_conf_t::coarsemaxstep, scif_gclk_opt_t::diven, scif_gclk_opt_t::divider, scif_gclk_opt_t::extosc_f, scif_dfll_closedloop_conf_t::finemaxstep, scif_dfll_closedloop_conf_t::fmul, scif_dfll_closedloop_conf_t::imul, scif_dfll0_closedloop_mainref_gc_enable, scif_dfll0_closedloop_start(), SCIF_DFLL_MAXFREQ_HZ, SCIF_DFLL_MINFREQ_HZ, SCIF_GCCTRL_CLK1K, SCIF_GCCTRL_OSC0, SCIF_GCCTRL_OSC32K, SCIF_GCCTRL_RC120M, SCIF_GCCTRL_RC32K, SCIF_GCCTRL_SLOWCLOCK, SCIF_RC120M_FREQ_HZ, SCIF_RC32K_FREQ_HZ, and SCIF_SLOWCLOCK_FREQ_HZ.

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void scif_start_rc120M ( void )

Start the 120MHz internal RCosc (RC120M) clock.

Calibration Functions Critical Path Oscillator Functions 120MHz RCosc Functions

References SCIF_UNLOCK.

void scif_stop_rc120M ( void )

Stop the 120MHz internal RCosc (RC120M) clock.

References SCIF_UNLOCK.

void scif_start_rc32k ( void )

Start the 32kHz internal RCosc (RC32K) clock.

32kHz internal RCosc (RC32K) Functions

References SCIF_UNLOCK.

void scif_stop_rc32k ( void )

Stop the 32kHz internal RCosc (RC32K) clock.

References SCIF_UNLOCK.

void scif_disable_rc32out ( void )

Unforce the RC32 signal from being output on the dedicated pin (PA20)

Referenced by scif_start_osc32().

long int scif_start_gclk	(	unsigned int	gclk,
		const scif_gclk_opt_t *	opt
	)

Setup and start a generic clock.

Parameters:

gclk	The generic clock number to setup and start (cf. datasheet)
opt	The settings for the generic clock.

Returns:: Status.

Return values:

0	Success.
<0	An error occured.

Generic Clock Functions

References scif_gclk_opt_t::clock_source, scif_gclk_opt_t::diven, scif_gclk_opt_t::divider, and SCIF_GCCTRL_OSCSEL_INVALID.

long int scif_stop_gclk ( unsigned int gclk )

Stop a generic clock.

Parameters:

gclk	The generic clock number to stop.

Note:: To avoid an infinite loop, this function checks the Clock enable flag SCIF_POLL_TIMEOUT times.

Returns:: Status.

Return values:

0	Success.
<0	Unable to stop generic clock.

References SCIF_POLL_TIMEOUT.

Referenced by scif_gc_setup().

long int scif_gc_setup	(	unsigned int	gclk,
		scif_gcctrl_oscsel_t	clk_src,
		unsigned int	diven,
		unsigned int	divfactor
	)

Setup a generic clock.

Parameters:

gclk	generic clock number (0 for gc0...)
clk_src	The input clock source to use for the generic clock
diven	Generic clock divisor enable
divfactor	Generic clock divisor

Note:: If the generic clock is already enabled, this function will disable it, apply the configuration then restart the generic clock.

Returns:: Status.

Return values:

0	Success.
<0	An error occured.

References SCIF_GCCTRL_OSCSEL_INVALID, and scif_stop_gclk().

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long int scif_gc_enable ( unsigned int gclk )

Enable a generic clock.

Parameters:

gclk	generic clock number (0 for gc0...)

Returns:: Status.

Return values:

0	Success.
<0	An error occured.

long int scif_pclksr_statushigh_wait ( unsigned long statusMask )

Wait for a status high in the Power and Clocks status register.

Parameters:

statusMask Mask field of the status to poll [INPUT]

Returns:: Status.

Return values:

0	Status is high.
<0	SCIF_POLL_TIMEOUT Timeout expired before the status was high.

Backup Registers Functions Misc

Parameters:

statusMask Mask field of the status to poll [INPUT]

Returns:: Status.

Return values:

0	Status is high.
<0	SCIF_POLL_TIMEOUT Timeout expired before the status was high.

References SCIF_POLL_TIMEOUT.

Referenced by scif_dfll0_closedloop_start(), scif_dfll0_openloop_start(), scif_dfll0_openloop_stop(), scif_dfll0_openloop_updatefreq(), scif_enable_osc(), scif_start_osc(), and scif_start_osc32().

Data Structures

Defines

Enumerations

OSC0/OSC1 Functions

OSC32 Functions

DFLL Control Functions

120MHz RCosc Functions

32kHz internal RCosc (RC32K) Functions

Generic Clock Functions

Miscellaneous Functions

Detailed Description

Define Documentation

Enumeration Type Documentation

Function Documentation