Nut/OS  5.0.5
API Reference
Data Structures | Defines
pm_uc3l.c File Reference
#include <avr32/io.h>
#include <arch/avr32.h>
#include <arch/avr32/pm.h>
#include <cfg/os.h>
#include <cfg/clock.h>
#include <dev/irqreg.h>
#include <sys/timer.h>
#include <arch/avr32/ihndlr.h>
#include "compiler.h"
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Data Structures

union  u_avr32_scif_oscctrl0_t
union  u_avr32_scif_oscctrl32_t
union  u_avr32_scif_dfll0conf_t
union  u_avr32_scif_dfll0ssg_t
struct  genclk_config
struct  dfll_config

Defines

#define SCIF_UNLOCK(reg)   (AVR32_SCIF.unlock = (AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET)|(reg))
 Unlock SCIF register macro.
#define SCIF_DFLL0_MODE_OPENLOOP   0
#define SCIF_DFLL0_MODE_CLOSEDLOOP   1
#define SCIF_DFLL_MINFREQ_KHZ   40000
 The min DFLL output frequency.
#define SCIF_DFLL_MINFREQ_HZ   40000000UL
#define SCIF_DFLL_MAXFREQ_KHZ   150000
 The max DFLL output frequency.
#define SCIF_DFLL_MAXFREQ_HZ   150000000UL
#define DFLL_COARSE_MAX   (AVR32_SCIF_COARSE_MASK >> AVR32_SCIF_COARSE_OFFSET)
#define DFLL_FINE_MAX   (AVR32_SCIF_FINE_MASK >> AVR32_SCIF_FINE_OFFSET)
#define DFLL_FINE_HALF   (1UL << (AVR32_SCIF_FINE_SIZE - 1))

System clock source

#define SYSCLK_SRC_RCSYS   0
 System RC oscillator.
#define SYSCLK_SRC_OSC0   1
 Oscillator 0.
#define SYSCLK_SRC_DFLL   2
 Digital Frequency Locked Loop.
#define SYSCLK_SRC_RC120M   3
 120 MHz RC oscillator
#define barrier()   asm volatile("" ::: "memory")
#define sysreg_write(reg, val)   __builtin_mtsr(reg, val)
#define sysreg_read(reg)   __builtin_mfsr(reg)
#define cpu_irq_disable()
#define dfll_write_reg(reg, value)
typedef uint32_t irqflags_t
void dfll_enable_open_loop (const struct dfll_config *cfg, unsigned int dfll_id)
void dfll_enable_closed_loop (const struct dfll_config *cfg, unsigned int dfll_id)
void sysclk_set_prescalers (unsigned int cpu_shift, unsigned int pba_shift, unsigned int pbb_shift)
 Set system clock prescaler configuration.
void pm_enable_osc0_crystal (unsigned int fosc0)
 This function will enable the crystal mode of the oscillator 0.
void sysclk_set_source (uint_fast8_t src)
 Change the source of the main system clock.
void pm_switch_to_osc0 (unsigned int fosc0, unsigned int startup)
 Switch main clock to clock Osc0 (crystal mode)
void Avr32InitClockTree (void)

Define Documentation

#define SCIF_UNLOCK (   reg)    (AVR32_SCIF.unlock = (AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET)|(reg))

Unlock SCIF register macro.

Referenced by dfll_enable_open_loop(), scif_configure_osc_crystalmode(), scif_configure_osc_extmode(), scif_dfll0_closedloop_start(), scif_dfll0_openloop_start(), scif_dfll0_openloop_stop(), scif_dfll0_openloop_updatefreq(), scif_dfll0_ssg_enable(), scif_enable_osc(), scif_start_osc(), scif_start_osc32(), scif_start_rc120M(), scif_start_rc32k(), scif_stop_osc(), scif_stop_osc32(), scif_stop_rc120M(), and scif_stop_rc32k().

#define SCIF_DFLL0_MODE_OPENLOOP   0
#define SCIF_DFLL0_MODE_CLOSEDLOOP   1
#define SCIF_DFLL_MINFREQ_KHZ   40000

The min DFLL output frequency.

Referenced by scif_dfll0_openloop_start_auto().

#define SCIF_DFLL_MINFREQ_HZ   40000000UL

Referenced by scif_dfll0_closedloop_configure_and_start().

#define SCIF_DFLL_MAXFREQ_KHZ   150000

The max DFLL output frequency.

Referenced by scif_dfll0_openloop_start_auto().

#define SCIF_DFLL_MAXFREQ_HZ   150000000UL

Referenced by scif_dfll0_closedloop_configure_and_start().

#define DFLL_COARSE_MAX   (AVR32_SCIF_COARSE_MASK >> AVR32_SCIF_COARSE_OFFSET)
#define DFLL_FINE_MAX   (AVR32_SCIF_FINE_MASK >> AVR32_SCIF_FINE_OFFSET)
#define DFLL_FINE_HALF   (1UL << (AVR32_SCIF_FINE_SIZE - 1))
#define SYSCLK_SRC_RCSYS   0

System RC oscillator.

#define SYSCLK_SRC_OSC0   1

Oscillator 0.

#define SYSCLK_SRC_DFLL   2

Digital Frequency Locked Loop.

Referenced by pm_switch_to_osc0().

#define SYSCLK_SRC_RC120M   3

120 MHz RC oscillator

#define barrier ( )    asm volatile("" ::: "memory")
#define sysreg_write (   reg,
  val 
)    __builtin_mtsr(reg, val)
#define sysreg_read (   reg)    __builtin_mfsr(reg)
#define cpu_irq_disable ( )
Value:
do {                                        \
        __builtin_ssrf(AVR32_SR_GM_OFFSET);     \
        barrier();                              \
    } while (0)
#define dfll_write_reg (   reg,
  value 
)
Value:
do {                                                                \
        irqflags_t dfll_flags;                                          \
        while (!(AVR32_SCIF.pclksr & AVR32_SCIF_DFLL0RDY_MASK));        \
        dfll_flags = cpu_irq_save();                                    \
        SCIF_UNLOCK(AVR32_SCIF_##reg);                                  \
        *(volatile uint32_t *)(AVR32_SCIF_ADDRESS + AVR32_SCIF_##reg)   \
                = (value);                                              \
        cpu_irq_restore(dfll_flags);                                    \
    } while (0)

Referenced by dfll_enable_closed_loop(), and dfll_enable_open_loop().

Typedef Documentation

typedef uint32_t irqflags_t

Function Documentation

void dfll_enable_open_loop ( const struct dfll_config *  cfg,
unsigned int  dfll_id 
)

References dfll_config::conf, dfll_write_reg, SCIF_UNLOCK, and dfll_config::ssg.

void dfll_enable_closed_loop ( const struct dfll_config *  cfg,
unsigned int  dfll_id 
)

References dfll_config::conf, dfll_write_reg, dfll_config::mul, dfll_config::ref_cfg, dfll_config::ssg, and dfll_config::step.

Referenced by pm_switch_to_osc0().

void sysclk_set_prescalers ( unsigned int  cpu_shift,
unsigned int  pba_shift,
unsigned int  pbb_shift 
)

Set system clock prescaler configuration.

This function will change the system clock prescaler configuration to match the parameters.

Note:
The parameters to this function are device-specific.
Parameters:
cpu_shiftThe CPU clock will be divided by $2^{cpu\_shift}$
pba_shiftThe PBA clock will be divided by $2^{pba\_shift}$
pbb_shiftThe PBB clock will be divided by $2^{pbb\_shift}$

Referenced by pm_switch_to_osc0().

void pm_enable_osc0_crystal ( unsigned int  fosc0)

This function will enable the crystal mode of the oscillator 0.

Parameters:
pmBase address of the Power Manager (i.e. &AVR32_PM)
fosc0Oscillator 0 crystal frequency (Hz)

Referenced by pm_switch_to_osc0().

void sysclk_set_source ( uint_fast8_t  src)

Change the source of the main system clock.

Parameters:
srcThe new system clock source. Must be one of the constants from the System Clock Sources section.

Referenced by pm_switch_to_osc0().

void pm_switch_to_osc0 ( unsigned int  fosc0,
unsigned int  startup 
)

Switch main clock to clock Osc0 (crystal mode)

Parameters:
pmBase address of the Power Manager (i.e. &AVR32_PM)
fosc0Oscillator 0 crystal frequency (Hz)
startupCrystal 0 startup time. AVR32_PM_OSCCTRL0_STARTUP_x_RCOSC.

References dfll_enable_closed_loop(), sysclk_set_prescalers(), sysclk_set_source(), and SYSCLK_SRC_DFLL.

Referenced by Avr32InitClockTree().

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void Avr32InitClockTree ( void  )

References pm_switch_to_osc0().

Referenced by NutInit().

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