System, AHB and APB busses clocks configuration functions.
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Detailed Description
System, AHB and APB busses clocks configuration functions.
===============================================================================
System, AHB and APB busses clocks configuration functions
===============================================================================
This section provide functions allowing to configure the System, AHB, APB1 and
APB2 busses clocks.
1. Several clock sources can be used to drive the System clock (SYSCLK): HSI,
HSE and PLL.
The AHB clock (HCLK) is derived from System clock through configurable prescaler
and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...).
APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through
configurable prescalers and used to clock the peripherals mapped on these busses.
You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
@note All the peripheral clocks are derived from the System clock (SYSCLK) except:
- I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
from an external clock mapped on the I2S_CKIN pin.
You have to use RCC_I2SCLKConfig() function to configure this clock.
- RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
functions to configure this clock.
- USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
to work correctly, while the SDIO require a frequency equal or lower than
to 48. This clock is derived of the main PLL through PLLQ divider.
- IWDG clock which is always the LSI clock.
2. The maximum frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz.
Depending on the device voltage range, the maximum frequency should be
adapted accordingly:
+-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
| |---------------------------------------------------------------------|
| | voltage range | voltage range | voltage range | voltage range |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
|---------------|----------------|----------------|-----------------|-----------------|
|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
|---------------|----------------|----------------|-----------------|-----------------|
|1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
|---------------|----------------|----------------|-----------------|-----------------|
|2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
|---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)| NA |96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
|---------------|----------------|----------------|-----------------|-----------------|
|5WS(6CPU cycle)| NA | NA |90 < HCLK <= 108 |80 < HCLK <= 96 |
|---------------|----------------|----------------|-----------------|-----------------|
|6WS(7CPU cycle)| NA | NA |108 < HCLK <= 120|96 < HCLK <= 112 |
|---------------|----------------|----------------|-----------------|-----------------|
|7WS(8CPU cycle)| NA | NA | NA |112 < HCLK <= 120|
+-------------------------------------------------------------------------------------+
===============================================================================
System, AHB and APB busses clocks configuration functions
===============================================================================
This section provide functions allowing to configure the System, AHB, APB1 and
APB2 busses clocks.
1. Several clock sources can be used to drive the System clock (SYSCLK): HSI,
HSE and PLL.
The AHB clock (HCLK) is derived from System clock through configurable prescaler
and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...).
APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through
configurable prescalers and used to clock the peripherals mapped on these busses.
You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
@note All the peripheral clocks are derived from the System clock (SYSCLK) except:
- I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
from an external clock mapped on the I2S_CKIN pin.
You have to use RCC_I2SCLKConfig() function to configure this clock.
- RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
functions to configure this clock.
- USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
to work correctly, while the SDIO require a frequency equal or lower than
to 48. This clock is derived of the main PLL through PLLQ divider.
- IWDG clock which is always the LSI clock.
2. The maximum frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 82 MHz and PCLK1 42 MHz.
Depending on the device voltage range, the maximum frequency should be
adapted accordingly:
+-------------------------------------------------------------------------------------+
| Latency | HCLK clock frequency (MHz) |
| |---------------------------------------------------------------------|
| | voltage range | voltage range | voltage range | voltage range |
| | 2.7 V - 3.6 V | 2.4 V - 2.7 V | 2.1 V - 2.4 V | 1.8 V - 2.1 V |
|---------------|----------------|----------------|-----------------|-----------------|
|0WS(1CPU cycle)|0 < HCLK <= 30 |0 < HCLK <= 24 |0 < HCLK <= 18 |0 < HCLK <= 16 |
|---------------|----------------|----------------|-----------------|-----------------|
|1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36 |16 < HCLK <= 32 |
|---------------|----------------|----------------|-----------------|-----------------|
|2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54 |32 < HCLK <= 48 |
|---------------|----------------|----------------|-----------------|-----------------|
|3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72 |48 < HCLK <= 64 |
|---------------|----------------|----------------|-----------------|-----------------|
|4WS(5CPU cycle)|120< HCLK <= 150|96 < HCLK <= 120|72 < HCLK <= 90 |64 < HCLK <= 80 |
|---------------|----------------|----------------|-----------------|-----------------|
|5WS(6CPU cycle)|120< HCLK <= 168|120< HCLK <= 144|90 < HCLK <= 108 |80 < HCLK <= 96 |
|---------------|----------------|----------------|-----------------|-----------------|
|6WS(7CPU cycle)| NA |144< HCLK <= 168|108 < HCLK <= 120|96 < HCLK <= 112 |
|---------------|----------------|----------------|-----------------|-----------------|
|7WS(8CPU cycle)| NA | NA |120 < HCLK <= 138|112 < HCLK <= 120|
+-------------------------------------------------------------------------------------+
@note When VOS bit (in PWR_CR register) is reset to '0’, the maximum value of HCLK is 144 MHz.
You can use PWR_MainRegulatorModeConfig() function to set or reset this bit.
===============================================================================
System, AHB and APB busses clocks configuration functions
===============================================================================
This section provide functions allowing to configure the System, AHB, APB1 and
APB2 busses clocks.
1. Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
HSE and PLL.
The AHB clock (HCLK) is derived from System clock through configurable prescaler
and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA and GPIO).
APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through
configurable prescalers and used to clock the peripherals mapped on these busses.
You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.
Note: All the peripheral clocks are derived from the System clock (SYSCLK) except:
==== - The USB 48 MHz clock which is derived from the PLL VCO clock.
- The ADC clock which is always the HSI clock. A divider by 1, 2 or 4 allows
to adapt the clock frequency to the device operating conditions.
- The RTC/LCD clock which is derived from the LSE, LSI or 1 MHz HSE_RTC (HSE
divided by a programmable prescaler).
The System clock (SYSCLK) frequency must be higher or equal to the RTC/LCD
clock frequency.
- IWDG clock which is always the LSI clock.
2. The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 32 MHz.
Depending on the device voltage range, the maximum frequency should be
adapted accordingly:
+----------------------------------------------------------------+
| Wait states | HCLK clock frequency (MHz) |
| |------------------------------------------------|
| (Latency) | voltage range | voltage range |
| | 1.65 V - 3.6 V | 2.0 V - 3.6 V |
| |----------------|---------------|---------------|
| | VCORE = 1.2 V | VCORE = 1.5 V | VCORE = 1.8 V |
|-------------- |----------------|---------------|---------------|
|0WS(1CPU cycle)|0 < HCLK <= 2 |0 < HCLK <= 8 |0 < HCLK <= 16 |
|---------------|----------------|---------------|---------------|
|1WS(2CPU cycle)|2 < HCLK <= 4 |8 < HCLK <= 16 |16 < HCLK <= 32|
+----------------------------------------------------------------+
3. After reset, the System clock source is the MSI (2 MHz) with 0 WS, Flash
32-bit access is enabled and prefetch is disabled.
It is recommended to use the following software sequences to tune the number
of wait states needed to access the Flash memory with the CPU frequency (HCLK).
- Increasing the CPU frequency (in the same voltage range)
- Program the Flash 64-bit access, using "FLASH_ReadAccess64Cmd(ENABLE)" function
- Check that 64-bit access is taken into account by reading FLASH_ACR
- Program Flash WS to 1, using "FLASH_SetLatency(FLASH_Latency_1)" function
- Check that the new number of WS is taken into account by reading FLASH_ACR
- Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
- If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
- Check that the new CPU clock source is taken into account by reading
the clock source status, using "RCC_GetSYSCLKSource()" function
- Decreasing the CPU frequency (in the same voltage range)
- Modify the CPU clock source, using "RCC_SYSCLKConfig()" function
- If needed, modify the CPU clock prescaler by using "RCC_HCLKConfig()" function
- Check that the new CPU clock source is taken into account by reading
the clock source status, using "RCC_GetSYSCLKSource()" function
- Program the new number of WS, using "FLASH_SetLatency()" function
- Check that the new number of WS is taken into account by reading FLASH_ACR
- Enable the Flash 32-bit access, using "FLASH_ReadAccess64Cmd(DISABLE)" function
- Check that 32-bit access is taken into account by reading FLASH_ACR
Function Documentation
| void RCC_SYSCLKConfig |
( |
uint32_t |
RCC_SYSCLKSource | ) |
|
Configures the system clock (SYSCLK).
- Note:
- The HSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
-
A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use RCC_GetSYSCLKSource() function to know which clock is currently used as system clock source.
- Parameters:
-
| RCC_SYSCLKSource,: | specifies the clock source used as system clock. This parameter can be one of the following values:
- RCC_SYSCLKSource_HSI: HSI selected as system clock source
- RCC_SYSCLKSource_HSE: HSE selected as system clock source
- RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
|
- Return values:
-
- Note:
- - The MSI is used (enabled by hardware) as system clock source after startup from Reset, wake-up from STOP and STANDBY mode, or in case of failure of the HSE used directly or indirectly as system clock (if the Clock Security System CSS is enabled).
- A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. You can use RCC_GetSYSCLKSource() function to know which clock is currently used as system clock source.
- Parameters:
-
| RCC_SYSCLKSource,: | specifies the clock source used as system clock source This parameter can be one of the following values:
- RCC_SYSCLKSource_MSI: MSI selected as system clock source
- RCC_SYSCLKSource_HSI: HSI selected as system clock source
- RCC_SYSCLKSource_HSE: HSE selected as system clock source
- RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
|
- Return values:
-
References assert_param, CFGR_SW_Mask, IS_RCC_SYSCLK_SOURCE, RCC, and RCC_CFGR_SW.
| uint8_t RCC_GetSYSCLKSource |
( |
void |
| ) |
|
Returns the clock source used as system clock.
- Parameters:
-
- Return values:
-
| The | clock source used as system clock. The returned value can be one of the following:
- 0x00: HSI used as system clock
- 0x04: HSE used as system clock
- 0x08: PLL used as system clock
|
- Parameters:
-
- Return values:
-
| The | clock source used as system clock. The returned value can be one of the following values:
- 0x00: MSI used as system clock
- 0x04: HSI used as system clock
- 0x08: HSE used as system clock
- 0x0C: PLL used as system clock
|
References CFGR_SWS_Mask, RCC, and RCC_CFGR_SWS.
| void RCC_HCLKConfig |
( |
uint32_t |
RCC_SYSCLK | ) |
|
Configures the AHB clock (HCLK).
- Note:
- Depending on the device voltage range, the software has to set correctly these bits to ensure that HCLK not exceed the maximum allowed frequency (for more details refer to section above "CPU, AHB and APB busses clocks configuration functions")
- Parameters:
-
| RCC_SYSCLK,: | defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:
- RCC_SYSCLK_Div1: AHB clock = SYSCLK
- RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
- RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
- RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
- RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
- RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
- RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
- RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
- RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
|
- Return values:
-
- Note:
- Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details refer to section above "CPU, AHB and APB busses clocks configuration functions")
- Parameters:
-
| RCC_SYSCLK,: | defines the AHB clock divider. This clock is derived from the system clock (SYSCLK). This parameter can be one of the following values:
- RCC_SYSCLK_Div1: AHB clock = SYSCLK
- RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
- RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
- RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
- RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
- RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
- RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
- RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
- RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
|
- Return values:
-
References assert_param, CFGR_HPRE_Reset_Mask, IS_RCC_HCLK, RCC, and RCC_CFGR_HPRE.
| void RCC_PCLK1Config |
( |
uint32_t |
RCC_HCLK | ) |
|
Configures the Low Speed APB clock (PCLK1).
- Parameters:
-
| RCC_HCLK,: | defines the APB1 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:
- RCC_HCLK_Div1: APB1 clock = HCLK
- RCC_HCLK_Div2: APB1 clock = HCLK/2
- RCC_HCLK_Div4: APB1 clock = HCLK/4
- RCC_HCLK_Div8: APB1 clock = HCLK/8
- RCC_HCLK_Div16: APB1 clock = HCLK/16
|
- Return values:
-
References assert_param, CFGR_PPRE1_Reset_Mask, IS_RCC_PCLK, RCC, and RCC_CFGR_PPRE1.
| void RCC_PCLK2Config |
( |
uint32_t |
RCC_HCLK | ) |
|
Configures the High Speed APB clock (PCLK2).
- Parameters:
-
| RCC_HCLK,: | defines the APB2 clock divider. This clock is derived from the AHB clock (HCLK). This parameter can be one of the following values:
- RCC_HCLK_Div1: APB2 clock = HCLK
- RCC_HCLK_Div2: APB2 clock = HCLK/2
- RCC_HCLK_Div4: APB2 clock = HCLK/4
- RCC_HCLK_Div8: APB2 clock = HCLK/8
- RCC_HCLK_Div16: APB2 clock = HCLK/16
|
- Return values:
-
References assert_param, CFGR_PPRE2_Reset_Mask, IS_RCC_PCLK, RCC, and RCC_CFGR_PPRE2.
Returns the frequencies of different on chip clocks; SYSCLK, HCLK, PCLK1 and PCLK2.
Returns the frequencies of different on chip clocks.
Returns the frequencies of the System, AHB and APB busses clocks.
- Note:
- The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
-
If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
-
If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
-
If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.
-
(*) HSI_VALUE is a constant defined in stm32f2xx.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.
-
(**) HSE_VALUE is a constant defined in stm32f2xx.h file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
-
The result of this function could be not correct when using fractional value for HSE crystal.
- Parameters:
-
| RCC_Clocks,: | pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies. |
- Note:
- This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.
-
Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update the structure's field. Otherwise, any configuration based on this function will be incorrect.
- Return values:
-
- Note:
- The system frequency computed by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the selected clock source:
-
If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
-
If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
-
If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) or HSI_VALUE(*) multiplied/divided by the PLL factors.
-
(*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature.
-
(**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value 25 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may have wrong result.
-
The result of this function could be not correct when using fractional value for HSE crystal.
- Parameters:
-
| RCC_Clocks,: | pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies. |
- Note:
- This function can be used by the user application to compute the baudrate for the communication peripherals or configure other parameters.
-
Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function must be called to update the structure's field. Otherwise, any configuration based on this function will be incorrect.
- Return values:
-
- Note:
- - The frequency returned by this function is not the real frequency in the chip. It is calculated based on the predefined constant and the source selected by RCC_SYSCLKConfig():
- If SYSCLK source is MSI, function returns constant the MSI value as defined by the MSI range, refer to RCC_MSIRangeConfig()
- If SYSCLK source is HSI, function returns constant HSI_VALUE(*)
(*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value 16 MHz) but the real value may vary depending on the variations in voltage and temperature, refer to RCC_AdjustHSICalibrationValue().
(**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value 8 MHz), user has to ensure that HSE_VALUE is same as the real frequency of the crystal used. Otherwise, this function may return wrong result.
- The result of this function could be not correct when using fractional value for HSE crystal.
- Parameters:
-
| RCC_Clocks,: | pointer to a RCC_ClocksTypeDef structure which will hold the clocks frequencies. |
- Return values:
-
References RCC_ClocksTypeDef::ADCCLK_Frequency, CFGR_ADCPRE_Set_Mask, CFGR_HPRE_Set_Mask, CFGR_PLLMull_Mask, CFGR_PLLSRC_Mask, CFGR_PLLXTPRE_Mask, CFGR_PPRE1_Set_Mask, CFGR_PPRE2_Set_Mask, CFGR_SWS_Mask, RCC_ClocksTypeDef::HCLK_Frequency, HSE_VALUE, HSI_VALUE, RCC_ClocksTypeDef::PCLK1_Frequency, RCC_ClocksTypeDef::PCLK2_Frequency, RCC, RCC_CFGR_HPRE, RCC_CFGR_PPRE1, RCC_CFGR_PPRE2, RCC_CFGR_SWS, RCC_PLLCFGR_PLLM, RCC_PLLCFGR_PLLN, RCC_PLLCFGR_PLLP, RCC_PLLCFGR_PLLSRC, RESET, and RCC_ClocksTypeDef::SYSCLK_Frequency.
Referenced by NutArchClockGet(), and USART_Init().
