Nut/OS  4.10.3
API Reference
at91sam7s.h
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00001 #ifndef _ARCH_ARM_SAM7S_H_
00002 #define _ARCH_ARM_SAM7S_H_
00003 /*
00004  * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
00005  *
00006  * Redistribution and use in source and binary forms, with or without
00007  * modification, are permitted provided that the following conditions
00008  * are met:
00009  *
00010  * 1. Redistributions of source code must retain the above copyright
00011  *    notice, this list of conditions and the following disclaimer.
00012  * 2. Redistributions in binary form must reproduce the above copyright
00013  *    notice, this list of conditions and the following disclaimer in the
00014  *    documentation and/or other materials provided with the distribution.
00015  * 3. Neither the name of the copyright holders nor the names of
00016  *    contributors may be used to endorse or promote products derived
00017  *    from this software without specific prior written permission.
00018  *
00019  * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
00020  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
00021  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
00022  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
00023  * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
00024  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
00025  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
00026  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
00027  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00028  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
00029  * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
00030  * SUCH DAMAGE.
00031  *
00032  * For additional information see http://www.ethernut.de/
00033  */
00034 
00054 #define FLASH_BASE      0x100000UL
00055 #define RAM_BASE        0x200000UL
00056 
00057 #define TC_BASE         0xFFFA0000      
00058 #define UDP_BASE        0xFFFB0000      
00059 #define TWI_BASE        0xFFFB8000      
00060 #define USART0_BASE     0xFFFC0000      
00061 #define USART1_BASE     0xFFFC4000      
00062 #define PWMC_BASE       0xFFFCC000      
00063 #define SSC_BASE        0xFFFD4000      
00064 #define ADC_BASE        0xFFFD8000      
00065 #define SPI0_BASE       0xFFFE0000      
00067 #define AIC_BASE        0xFFFFF000      
00068 #define DBGU_BASE       0xFFFFF200      
00069 #define PIOA_BASE       0xFFFFF400      
00070 #define PMC_BASE        0xFFFFFC00      
00071 #define RSTC_BASE       0xFFFFFD00      
00072 #define RTT_BASE        0xFFFFFD20      
00073 #define PIT_BASE        0xFFFFFD30      
00074 #define WDT_BASE        0xFFFFFD40      
00075 #define VREG_BASE       0xFFFFFD60      
00076 #define MC_BASE         0xFFFFFF00      
00078 #define PERIPH_RPR_OFF  0x00000100      
00079 #define PERIPH_RCR_OFF  0x00000104      
00080 #define PERIPH_TPR_OFF  0x00000108      
00081 #define PERIPH_TCR_OFF  0x0000010C      
00082 #define PERIPH_RNPR_OFF 0x00000110      
00083 #define PERIPH_RNCR_OFF 0x00000114      
00084 #define PERIPH_TNPR_OFF 0x00000118      
00085 #define PERIPH_TNCR_OFF 0x0000011C      
00086 #define PERIPH_PTCR_OFF 0x00000120      
00087 #define PERIPH_PTSR_OFF 0x00000124      
00089 #define PDC_RXTEN       0x00000001      
00090 #define PDC_RXTDIS      0x00000002      
00091 #define PDC_TXTEN       0x00000100      
00092 #define PDC_TXTDIS      0x00000200      
00094 #define DBGU_HAS_PDC
00095 #define SPI_HAS_PDC
00096 #define SSC_HAS_PDC
00097 #define USART_HAS_PDC
00098 #define USART_HAS_MODE
00099 
00100 #define PIO_HAS_MULTIDRIVER
00101 #define PIO_HAS_PULLUP
00102 #define PIO_HAS_PERIPHERALSELECT
00103 #define PIO_HAS_OUTPUTWRITEENABLE
00104 
00105 #include <arch/arm/atmel/at91_tc.h>
00106 #include <arch/arm/atmel/at91_pwmc.h>
00107 #include <arch/arm/atmel/at91_us.h>
00108 #include <arch/arm/atmel/at91_dbgu.h>
00109 #include <arch/arm/atmel/at91_spi.h>
00110 #include <arch/arm/atmel/at91_aic.h>
00111 #include <arch/arm/atmel/at91_pio.h>
00112 #include <arch/arm/atmel/at91_pmc.h>
00113 #include <arch/arm/atmel/at91_rstc.h>
00114 #include <arch/arm/atmel/at91_wdt.h>
00115 #include <arch/arm/atmel/at91_pit.h>
00116 #include <arch/arm/atmel/at91_mc.h>
00117 #include <arch/arm/atmel/at91_ssc.h>
00118 #include <arch/arm/atmel/at91_twi.h>
00119 #include <arch/arm/atmel/at91_adc.h>
00120 
00123 
00126 #define FIQ_ID      0       
00127 #define SYSC_ID     1       
00128 #define PIOA_ID     2       
00129 /* Reserved         3*/
00130 #define ADC_ID      4       
00131 #define SPI0_ID     5       
00132 #define US0_ID      6       
00133 #define US1_ID      7       
00134 #define SSC_ID      8       
00135 #define TWI_ID      9       
00136 #define PWMC_ID     10      
00137 #define UDP_ID      11      
00138 #define TC0_ID      12      
00139 #define TC1_ID      13      
00140 #define TC2_ID      14      
00141 /* Reserved      15-29*/
00142 #define IRQ0_ID     30      
00143 #define IRQ1_ID     31      
00145 
00146 
00148 #define SPI0_NPCS0_PA11A        11      
00149 #define SPI0_NPCS1_PA09B        9       
00150 #define SPI0_NPCS1_PA31A        31      
00151 #define SPI0_NPCS2_PA10B        10      
00152 #define SPI0_NPCS2_PA30B        30      
00153 #define SPI0_NPCS3_PA03B        3       
00154 #define SPI0_NPCS3_PA05B        5       
00155 #define SPI0_NPCS3_PA22B        22      
00156 #define SPI0_MISO_PA12A    12 
00157 #define SPI0_MOSI_PA13A    13 
00158 #define SPI0_SPCK_PA14A    14 
00160 
00161 
00163 #define PA5_RXD0_A          5
00164 #define PA6_TXD0_A          6
00165 #define PA2_SCK0_B          2
00166 #define PA7_RTS0_A          7
00167 #define PA8_CTS0_A          8
00168 
00169 #define PA21_RXD1_A         21
00170 #define PA22_TXD1_A         22
00171 #define PA23_SCK1_A         23
00172 #define PA24_RTS1_A         24
00173 #define PA25_CTS1_A         25
00174 #define PB26_DCD1_A         26
00175 #define PB28_DSR1_A         28
00176 #define PB27_DTR1_A         27
00177 #define PB29_RI1_A          29
00178 
00182 #define PA12_SPI0_MISO_A    12
00183 #define PA13_SPI0_MOSI_A    13
00184 #define PA14_SPI0_SPCK_A    14
00185 #define PA11_SPI0_NPCS0_A   11
00186 #define PA9_SPI0_NPCS1_B    9
00187 #define PA31_SPI0_NPCS1_A   31
00188 #define PA10_SPI0_NPCS2_B   10
00189 #define PB30_SPI0_NPCS2_B   30
00190 #define PA3_SPI0_NPCS3_B    3
00191 #define PA5_SPI0_NPCS3_B    5
00192 #define PA22_SPI0_NPCS3_B   22
00193 
00194 #define SPI0_PINS           _BV(PA12_SPI0_MISO_A) | _BV(PA13_SPI0_MOSI_A) | _BV(PA14_SPI0_SPCK_A)
00195 #define SPI0_PIO_BASE       PIOA_BASE
00196 #define SPI0_PSR_OFF        PIO_ASR_OFF
00197 
00198 #define SPI0_CS0_PIN        _BV(PA11_SPI0_NPCS0_A)
00199 #define SPI0_CS0_PIO_BASE   PIOA_BASE
00200 #define SPI0_CS0_PSR_OFF    PIO_ASR_OFF
00201 
00202 #ifndef SPI0_CS1_PIN
00203 #define SPI0_CS1_PIN        _BV(PA9_SPI0_NPCS1_B)
00204 #define SPI0_CS1_PIO_BASE   PIOA_BASE
00205 #define SPI0_CS1_PSR_OFF    PIO_ASR_OFF
00206 #endif
00207 
00208 #ifndef SPI0_CS2_PIN
00209 #define SPI0_CS2_PIN        _BV(PA10_SPI0_NPCS2_B)
00210 #define SPI0_CS2_PIO_BASE   PIOA_BASE
00211 #define SPI0_CS2_PSR_OFF    PIO_ASR_OFF
00212 #endif
00213 
00214 #ifndef SPI0_CS3_PIN
00215 #define SPI0_CS3_PIN        _BV(PA3_SPI0_NPCS3_B)
00216 #define SPI0_CS3_PIO_BASE   PIOA_BASE
00217 #define SPI0_CS3_PSR_OFF    PIO_ASR_OFF
00218 #endif
00219 
00224 #define PA9_DRXD_A          9
00225 #define PA10_DTXD_A         10
00226 
00230 #define PA17_TD_A           17  
00231 #define PA18_RD_A           18  
00232 #define PA16_TK_A           16  
00233 #define PA19_RK_A           19  
00234 #define PA15_TF_A           15  
00235 #define PA20_RF_A           20  
00237 
00238 
00240 #define PA3_TWD_A          3  
00241 #define PA4_TWCK_A         4  
00243 
00244 
00246 #define PA0_TIOA0_B        0
00247 #define PA1_TIOB0_B        1
00248 #define PA4_TCLK0_B        4
00249 
00250 #define PA15_TIOA1_B        15
00251 #define PA16_TIOB1_B        16
00252 #define PA28_TCLK1_B        28
00253 
00254 #define PA26_TIOA2_B        26
00255 #define PA27_TIOB2_B        27
00256 #define PA29_TCLK2_B        29
00257 
00261 #define PA6_PCK0_B          6
00262 #define PA17_PCK1_B         17
00263 #define PA21_PCK1_B         21
00264 #define PA18_PCK2_B         18
00265 #define PA31_PCK2_B         31
00266 
00270 #define PA19_FIQ_B          19
00271 #define PA20_IRQ0_B         20
00272 #define PA30_IRQ1_A         30
00273 
00277 #define PA8_ADTRG_B        8  
00279 
00280 
00282 #define PA0_PWM0_A          0
00283 #define PA23_PWM0_B         23
00284 #define PA1_PWM1_A          1
00285 #define PA24_PWM1_B         24
00286 #define PA2_PWM2_A          2
00287 #define PA13_PWM2_B         13
00288 #define PA25_PWM2_B         25
00289 #define PA7_PWM3_B          7
00290 #define PA14_PWM3_B         14
00291 
00293 
00295 #endif                          /* _ARCH_ARM_AT91SAM7S_H_ */